Lines Matching +full:phy +full:- +full:ref +full:- +full:clk
1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Felipe Balbi <balbi@kernel.org>
14 be presented as a standalone DT node with an optional vendor-specific
18 - $ref: usb-drd.yaml#
19 - if:
25 - dr_mode
27 $ref: usb.yaml#
29 $ref: usb-xhci.yaml#
35 - const: snps,dwc3
36 - const: synopsys,dwc3
49 interrupt-names:
53 - const: dwc_usb3
54 - items:
60 SoC Bus Clock (AHB/AXI/Native). ref generates ITP when the UTMI/ULPI
61 PHY is suspended. suspend clocks a small part of the USB3 core when
62 SS PHY in P3. But particular cases may differ from that having less
65 clock-names:
68 - enum: [bus_early, ref, suspend]
69 - true
71 dma-coherent: true
80 usb-phy:
83 - description: USB2/HS PHY
84 - description: USB3/SS PHY
90 phy-names:
95 - usb2-phy
96 - usb3-phy
98 power-domains:
100 The DWC3 has 2 power-domains. The power management unit (PMU) and
105 - description: Core
106 - description: Power management unit
111 snps,usb2-lpm-disable:
120 snps,usb2-gadget-lpm-disable:
125 snps,dis-start-transfer-quirk:
127 When set, disable isoc START TRANSFER command failure SW work-around
128 for DWC_usb31 version 1.70a-ea06 and prior.
137 snps,has-lpm-erratum:
141 snps,lpm-nyet-threshold:
143 $ref: /schemas/types.yaml#/definitions/uint8
165 description: When set core will delay PHY power change from P0 to P1/P2/P3.
179 description: When set core will set Tx de-emphasis value
184 The value driven to the PHY is controlled by the LTSSM during USB3
186 $ref: /schemas/types.yaml#/definitions/uint8
188 - 0 # -6dB de-emphasis
189 - 1 # -3.5dB de-emphasis
190 - 2 # No de-emphasis
193 description: When set core will disable USB3 suspend phy
197 description: When set core will disable USB2 suspend phy
203 to the PHY.
206 snps,dis-u1-entry-quirk:
210 snps,dis-u2-entry-quirk:
216 When set core will disable receiver detection in PHY P3 power state.
219 snps,dis-u2-freeclk-exists-quirk:
222 PHY doesn't provide a free-running PHY clock.
225 snps,dis-del-phy-power-chg-quirk:
227 When set core will change PHY power from P0 to P1/P2/P3 without delay.
230 snps,dis-tx-ipgap-linecheck-quirk:
234 snps,parkmode-disable-ss-quirk:
239 snps,parkmode-disable-hs-quirk:
250 snps,dis-split-quirk:
253 avoid -EPROTO errors with usbhid on some devices (Hikey 970).
256 snps,gfladj-refclk-lpm-sel-quirk:
261 snps,resume-hs-terminations:
268 snps,ulpi-ext-vbus-drv:
270 Some ULPI USB PHY does not support internal VBUS supply, and driving
272 bit. When set, the xhci host will configure the USB2 PHY drives VBUS
276 snps,is-utmi-l1-suspend:
282 snps,hird-threshold:
284 $ref: /schemas/types.yaml#/definitions/uint8
288 High-Speed PHY interface selection between UTMI+ and ULPI when the
290 $ref: /schemas/types.yaml#/definitions/string
293 snps,quirk-frame-length-adjustment:
295 Value for GFLADJ_30MHZ field of GFLADJ register for post-silicon frame
298 $ref: /schemas/types.yaml#/definitions/uint32
302 snps,ref-clock-period-ns:
313 snps,rx-thr-num-pkt:
320 flow-controlled endpoint. It is only used for SuperSpeed.
323 $ref: /schemas/types.yaml#/definitions/uint8
327 snps,rx-max-burst:
339 $ref: /schemas/types.yaml#/definitions/uint8
343 snps,tx-thr-num-pkt:
352 $ref: /schemas/types.yaml#/definitions/uint8
356 snps,tx-max-burst:
365 $ref: /schemas/types.yaml#/definitions/uint8
369 snps,rx-thr-num-pkt-prd:
372 snps,rx-max-burst-prd to a valid, non-zero value 1-16 (DWC_usb31
374 $ref: /schemas/types.yaml#/definitions/uint8
378 snps,rx-max-burst-prd:
381 snps,rx-thr-num-pkt-prd to a valid, non-zero value 1-16 (DWC_usb31
383 $ref: /schemas/types.yaml#/definitions/uint8
387 snps,tx-thr-num-pkt-prd:
390 snps,tx-max-burst-prd to a valid, non-zero value 1-16 (DWC_usb31
392 $ref: /schemas/types.yaml#/definitions/uint8
396 snps,tx-max-burst-prd:
399 snps,tx-thr-num-pkt-prd to a valid, non-zero value 1-16 (DWC_usb31
401 $ref: /schemas/types.yaml#/definitions/uint8
405 tx-fifo-resize:
413 tx-fifo-max-num:
418 $ref: /schemas/types.yaml#/definitions/uint8
421 snps,incr-burst-type-adjustment:
428 $ref: /schemas/types.yaml#/definitions/uint32-array
435 num-hc-interrupters:
440 $ref: /schemas/graph.yaml#/properties/port
442 This port is used with the 'usb-role-switch' property to connect the
446 $ref: /schemas/graph.yaml#/properties/ports
449 controller using the OF graph bindings specified if the "usb-role-switch"
454 $ref: /schemas/graph.yaml#/properties/port
458 $ref: /schemas/graph.yaml#/properties/port
461 wakeup-source:
462 $ref: /schemas/types.yaml#/definitions/flag
469 - compatible
470 - reg
471 - interrupts
474 - |
479 usb-phy = <&usb2_phy>, <&usb3_phy>;
480 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
482 - |
487 clocks = <&clk 1>, <&clk 2>, <&clk 3>;
488 clock-names = "bus_early", "ref", "suspend";
490 phy-names = "usb2-phy", "usb3-phy";