Lines Matching +full:gcc +full:- +full:sm8150
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wesley Cheng <quic_wcheng@quicinc.com>
15 - enum:
16 - qcom,ipq4019-dwc3
17 - qcom,ipq5018-dwc3
18 - qcom,ipq5332-dwc3
19 - qcom,ipq6018-dwc3
20 - qcom,ipq8064-dwc3
21 - qcom,ipq8074-dwc3
22 - qcom,ipq9574-dwc3
23 - qcom,msm8953-dwc3
24 - qcom,msm8994-dwc3
25 - qcom,msm8996-dwc3
26 - qcom,msm8998-dwc3
27 - qcom,qcm2290-dwc3
28 - qcom,qcs404-dwc3
29 - qcom,sa8775p-dwc3
30 - qcom,sc7180-dwc3
31 - qcom,sc7280-dwc3
32 - qcom,sc8280xp-dwc3
33 - qcom,sdm660-dwc3
34 - qcom,sdm670-dwc3
35 - qcom,sdm845-dwc3
36 - qcom,sdx55-dwc3
37 - qcom,sdx65-dwc3
38 - qcom,sdx75-dwc3
39 - qcom,sm4250-dwc3
40 - qcom,sm6115-dwc3
41 - qcom,sm6125-dwc3
42 - qcom,sm6350-dwc3
43 - qcom,sm6375-dwc3
44 - qcom,sm8150-dwc3
45 - qcom,sm8250-dwc3
46 - qcom,sm8350-dwc3
47 - qcom,sm8450-dwc3
48 - qcom,sm8550-dwc3
49 - qcom,sm8650-dwc3
50 - qcom,x1e80100-dwc3
51 - const: qcom,dwc3
57 "#address-cells":
60 "#size-cells":
65 power-domains:
69 required-opps:
75 - cfg_noc:: System Config NOC clock.
76 - core:: Master/Core clock, has to be >= 125 MHz for SS operation and >=
78 - iface:: System bus AXI clock.
79 - sleep:: Sleep clock, used for wakeup when USB3 core goes into low
81 - mock_utmi:: Mock utmi clock needed for ITP/SOF generation in host
86 clock-names:
96 interconnect-names:
98 - const: usb-ddr
99 - const: apps-usb
104 - pwr_event: Used for wakeup based on other power events.
105 - hs_phY_irq: Apart from DP/DM/QUSB2 PHY interrupts, there is
109 - qusb2_phy: SoCs with QUSB2 PHY do not have separate DP/DM IRQs and
114 - {dp/dm}_hs_phy_irq: These IRQ's directly reflect changes on the DP/
116 only on SoCs with non-QUSB2 targets with
118 - ss_phy_irq: Used for remote wakeup in Super Speed mode of operation.
122 interrupt-names:
126 qcom,select-utmi-as-pipe-clk:
133 wakeup-source: true
138 "^usb@[0-9a-f]+$":
143 wakeup-source: false
146 - compatible
147 - reg
148 - "#address-cells"
149 - "#size-cells"
150 - ranges
151 - clocks
152 - clock-names
153 - interrupts
154 - interrupt-names
157 - if:
162 - qcom,ipq4019-dwc3
167 clock-names:
169 - const: core
170 - const: sleep
171 - const: mock_utmi
173 - if:
178 - qcom,ipq8064-dwc3
183 - description: Master/Core clock, has to be >= 125 MHz
185 clock-names:
187 - const: core
189 - if:
194 - qcom,ipq9574-dwc3
195 - qcom,msm8953-dwc3
196 - qcom,msm8996-dwc3
197 - qcom,msm8998-dwc3
198 - qcom,sa8775p-dwc3
199 - qcom,sc7180-dwc3
200 - qcom,sc7280-dwc3
201 - qcom,sdm670-dwc3
202 - qcom,sdm845-dwc3
203 - qcom,sdx55-dwc3
204 - qcom,sdx65-dwc3
205 - qcom,sdx75-dwc3
206 - qcom,sm6350-dwc3
211 clock-names:
213 - const: cfg_noc
214 - const: core
215 - const: iface
216 - const: sleep
217 - const: mock_utmi
219 - if:
224 - qcom,ipq6018-dwc3
230 clock-names:
232 - items:
233 - const: core
234 - const: sleep
235 - const: mock_utmi
236 - items:
237 - const: cfg_noc
238 - const: core
239 - const: sleep
240 - const: mock_utmi
242 - if:
247 - qcom,ipq8074-dwc3
252 clock-names:
254 - const: cfg_noc
255 - const: core
256 - const: sleep
257 - const: mock_utmi
259 - if:
264 - qcom,ipq5018-dwc3
265 - qcom,ipq5332-dwc3
266 - qcom,msm8994-dwc3
267 - qcom,qcs404-dwc3
272 clock-names:
274 - const: core
275 - const: iface
276 - const: sleep
277 - const: mock_utmi
279 - if:
284 - qcom,sc8280xp-dwc3
285 - qcom,x1e80100-dwc3
290 clock-names:
292 - const: cfg_noc
293 - const: core
294 - const: iface
295 - const: sleep
296 - const: mock_utmi
297 - const: noc_aggr
298 - const: noc_aggr_north
299 - const: noc_aggr_south
300 - const: noc_sys
302 - if:
307 - qcom,sdm660-dwc3
313 clock-names:
315 - items:
316 - const: cfg_noc
317 - const: core
318 - const: iface
319 - const: sleep
320 - const: mock_utmi
321 - items:
322 - const: cfg_noc
323 - const: core
324 - const: sleep
325 - const: mock_utmi
327 - if:
332 - qcom,qcm2290-dwc3
333 - qcom,sm6115-dwc3
334 - qcom,sm6125-dwc3
335 - qcom,sm8150-dwc3
336 - qcom,sm8250-dwc3
337 - qcom,sm8450-dwc3
338 - qcom,sm8550-dwc3
339 - qcom,sm8650-dwc3
344 clock-names:
346 - const: cfg_noc
347 - const: core
348 - const: iface
349 - const: sleep
350 - const: mock_utmi
351 - const: xo
353 - if:
358 - qcom,sm8350-dwc3
364 clock-names:
367 - const: cfg_noc
368 - const: core
369 - const: iface
370 - const: sleep
371 - const: mock_utmi
372 - const: xo
374 - if:
379 - qcom,ipq5018-dwc3
380 - qcom,ipq6018-dwc3
381 - qcom,ipq8074-dwc3
382 - qcom,msm8953-dwc3
383 - qcom,msm8998-dwc3
389 interrupt-names:
391 - const: pwr_event
392 - const: qusb2_phy
393 - const: ss_phy_irq
395 - if:
400 - qcom,msm8996-dwc3
401 - qcom,qcs404-dwc3
402 - qcom,sdm660-dwc3
403 - qcom,sm6115-dwc3
404 - qcom,sm6125-dwc3
410 interrupt-names:
412 - const: pwr_event
413 - const: qusb2_phy
414 - const: hs_phy_irq
415 - const: ss_phy_irq
417 - if:
422 - qcom,ipq5332-dwc3
423 - qcom,x1e80100-dwc3
428 interrupt-names:
430 - const: pwr_event
431 - const: dp_hs_phy_irq
432 - const: dm_hs_phy_irq
433 - const: ss_phy_irq
435 - if:
440 - qcom,ipq4019-dwc3
441 - qcom,ipq8064-dwc3
442 - qcom,msm8994-dwc3
443 - qcom,sa8775p-dwc3
444 - qcom,sc7180-dwc3
445 - qcom,sc7280-dwc3
446 - qcom,sc8280xp-dwc3
447 - qcom,sdm670-dwc3
448 - qcom,sdm845-dwc3
449 - qcom,sdx55-dwc3
450 - qcom,sdx65-dwc3
451 - qcom,sdx75-dwc3
452 - qcom,sm4250-dwc3
453 - qcom,sm6350-dwc3
454 - qcom,sm8150-dwc3
455 - qcom,sm8250-dwc3
456 - qcom,sm8350-dwc3
457 - qcom,sm8450-dwc3
458 - qcom,sm8550-dwc3
459 - qcom,sm8650-dwc3
465 interrupt-names:
467 - const: pwr_event
468 - const: hs_phy_irq
469 - const: dp_hs_phy_irq
470 - const: dm_hs_phy_irq
471 - const: ss_phy_irq
476 - |
477 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
478 #include <dt-bindings/interrupt-controller/arm-gic.h>
479 #include <dt-bindings/interrupt-controller/irq.h>
481 #address-cells = <2>;
482 #size-cells = <2>;
485 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
488 #address-cells = <2>;
489 #size-cells = <2>;
491 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
492 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
493 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
494 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
495 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
496 clock-names = "cfg_noc",
502 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
503 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
504 assigned-clock-rates = <19200000>, <150000000>;
511 interrupt-names = "pwr_event", "hs_phy_irq",
514 power-domains = <&gcc USB30_PRIM_GDSC>;
516 resets = <&gcc GCC_USB30_PRIM_BCR>;
526 phy-names = "usb2-phy", "usb3-phy";