Lines Matching +full:zynqmp +full:- +full:power
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/dwc3-xilinx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mubin Sayyed <mubin.sayyed@amd.com>
11 - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
16 - enum:
17 - xlnx,zynqmp-dwc3
18 - xlnx,versal-dwc3
22 "#address-cells":
25 "#size-cells":
30 power-domains:
36 A list of phandle and clock-specifier pairs for the clocks
37 listed in clock-names.
39 - description: Master/Core clock, has to be >= 125 MHz
41 - description: Clock source to core during PHY power down.
43 clock-names:
45 - const: bus_clk
46 - const: ref_clk
50 A list of phandles for resets listed in reset-names.
53 - description: USB core reset
54 - description: USB hibernation reset
55 - description: USB APB reset
57 reset-names:
59 - const: usb_crst
60 - const: usb_hibrst
61 - const: usb_apbrst
67 phy-names:
72 - usb2-phy
73 - usb3-phy
75 reset-gpios:
76 description: GPIO used for the reset ulpi-phy
82 "^usb@[0-9a-f]+$":
86 - compatible
87 - reg
88 - "#address-cells"
89 - "#size-cells"
90 - ranges
91 - power-domains
92 - clocks
93 - clock-names
94 - resets
95 - reset-names
100 - |
101 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
102 #include <dt-bindings/power/xlnx-zynqmp-power.h>
103 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
104 #include <dt-bindings/clock/xlnx-zynqmp-clk.h>
105 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
106 #include <dt-bindings/phy/phy.h>
108 #address-cells = <2>;
109 #size-cells = <2>;
112 #address-cells = <0x2>;
113 #size-cells = <0x2>;
114 compatible = "xlnx,zynqmp-dwc3";
117 clock-names = "bus_clk", "ref_clk";
118 power-domains = <&zynqmp_firmware PD_USB_0>;
122 reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
124 phy-names = "usb3-phy";
130 interrupt-names = "host", "otg";
133 dma-coherent;