Lines Matching +full:ufshc +full:- +full:m31 +full:- +full:16 +full:nm
1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/ufs/ti,j721e-ufs.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vignesh Raghavendra <vigneshr@ti.com>
15 - const: ti,j721e-ufs
23 description: phandle to the M-PHY clock
25 power-domains:
28 assigned-clocks:
31 assigned-clock-parents:
34 "#address-cells":
37 "#size-cells":
43 - compatible
44 - reg
45 - clocks
46 - power-domains
49 "^ufs@[0-9a-f]+$":
50 $ref: cdns,ufshc.yaml
58 - |
59 #include <dt-bindings/interrupt-controller/irq.h>
60 #include <dt-bindings/interrupt-controller/arm-gic.h>
63 #address-cells = <2>;
64 #size-cells = <2>;
66 ufs-wrapper@4e80000 {
67 compatible = "ti,j721e-ufs";
69 power-domains = <&k3_pds 277>;
71 assigned-clocks = <&k3_clks 277 1>;
72 assigned-clock-parents = <&k3_clks 277 4>;
75 #address-cells = <2>;
76 #size-cells = <2>;
79 compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0";
82 freq-table-hz = <19200000 19200000>;
83 power-domains = <&k3_pds 277>;
85 assigned-clocks = <&k3_clks 277 1>;
86 assigned-clock-parents = <&k3_clks 277 4>;
87 clock-names = "core_clk";