Lines Matching +full:sm8450 +full:- +full:tlmm
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
11 - Andy Gross <agross@kernel.org>
13 # Select only our matches, not all jedec,ufs-2.0
20 - compatible
25 - enum:
26 - qcom,msm8994-ufshc
27 - qcom,msm8996-ufshc
28 - qcom,msm8998-ufshc
29 - qcom,sa8775p-ufshc
30 - qcom,sc7280-ufshc
31 - qcom,sc8280xp-ufshc
32 - qcom,sdm845-ufshc
33 - qcom,sm6115-ufshc
34 - qcom,sm6350-ufshc
35 - qcom,sm8150-ufshc
36 - qcom,sm8250-ufshc
37 - qcom,sm8350-ufshc
38 - qcom,sm8450-ufshc
39 - qcom,sm8550-ufshc
40 - qcom,sm8650-ufshc
41 - const: qcom,ufshc
42 - const: jedec,ufs-2.0
48 clock-names:
52 dma-coherent: true
58 interconnect-names:
60 - const: ufs-ddr
61 - const: cpu-ufs
70 phy-names:
72 - const: ufsphy
74 power-domains:
85 reg-names:
87 - const: std
88 - const: ice
90 required-opps:
96 '#reset-cells':
99 reset-names:
101 - const: rst
103 reset-gpios:
109 - compatible
110 - reg
113 - $ref: ufs-common.yaml
115 - if:
120 - qcom,msm8998-ufshc
121 - qcom,sa8775p-ufshc
122 - qcom,sc7280-ufshc
123 - qcom,sc8280xp-ufshc
124 - qcom,sm8250-ufshc
125 - qcom,sm8350-ufshc
126 - qcom,sm8450-ufshc
127 - qcom,sm8550-ufshc
128 - qcom,sm8650-ufshc
134 clock-names:
136 - const: core_clk
137 - const: bus_aggr_clk
138 - const: iface_clk
139 - const: core_clk_unipro
140 - const: ref_clk
141 - const: tx_lane0_sync_clk
142 - const: rx_lane0_sync_clk
143 - const: rx_lane1_sync_clk
147 reg-names:
150 - if:
155 - qcom,sdm845-ufshc
156 - qcom,sm6350-ufshc
157 - qcom,sm8150-ufshc
163 clock-names:
165 - const: core_clk
166 - const: bus_aggr_clk
167 - const: iface_clk
168 - const: core_clk_unipro
169 - const: ref_clk
170 - const: tx_lane0_sync_clk
171 - const: rx_lane0_sync_clk
172 - const: rx_lane1_sync_clk
173 - const: ice_core_clk
177 reg-names:
180 - reg-names
182 - if:
187 - qcom,msm8996-ufshc
193 clock-names:
195 - const: core_clk_src
196 - const: core_clk
197 - const: bus_clk
198 - const: bus_aggr_clk
199 - const: iface_clk
200 - const: core_clk_unipro_src
201 - const: core_clk_unipro
202 - const: core_clk_ice
203 - const: ref_clk
204 - const: tx_lane0_sync_clk
205 - const: rx_lane0_sync_clk
209 reg-names:
212 - if:
217 - qcom,sm6115-ufshc
223 clock-names:
225 - const: core_clk
226 - const: bus_aggr_clk
227 - const: iface_clk
228 - const: core_clk_unipro
229 - const: ref_clk
230 - const: tx_lane0_sync_clk
231 - const: rx_lane0_sync_clk
232 - const: ice_core_clk
236 reg-names:
239 - reg-names
241 # TODO: define clock bindings for qcom,msm8994-ufshc
243 - if:
245 - qcom,ice
265 - |
266 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
267 #include <dt-bindings/clock/qcom,rpmh.h>
268 #include <dt-bindings/gpio/gpio.h>
269 #include <dt-bindings/interconnect/qcom,sm8450.h>
270 #include <dt-bindings/interrupt-controller/arm-gic.h>
273 #address-cells = <2>;
274 #size-cells = <2>;
277 compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
278 "jedec,ufs-2.0";
282 phy-names = "ufsphy";
283 lanes-per-direction = <2>;
284 #reset-cells = <1>;
286 reset-names = "rst";
287 reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
289 vcc-supply = <&vreg_l7b_2p5>;
290 vcc-max-microamp = <1100000>;
291 vccq-supply = <&vreg_l9b_1p2>;
292 vccq-max-microamp = <1200000>;
294 power-domains = <&gcc UFS_PHY_GDSC>;
298 interconnect-names = "ufs-ddr", "cpu-ufs";
300 clock-names = "core_clk",
316 freq-table-hz = <75000000 300000000>,