Lines Matching +full:hart +full:- +full:compatible
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Palmer Dabbelt <palmer@dabbelt.com>
11 - Anup Patel <anup.patel@wdc.com>
14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive
15 Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
16 interrupts. It directly connects to the timer and inter-processor interrupt
17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
19 The clock frequency of CLINT is specified via "timebase-frequency" DT
20 property of "/cpus" DT node. The "timebase-frequency" DT property is
23 T-Head C906/C910 CPU cores include an implementation of CLINT too, however
24 their implementation lacks a memory-mapped MTIME register, thus not
25 compatible with SiFive ones.
28 compatible:
30 - items:
31 - enum:
32 - canaan,k210-clint # Canaan Kendryte K210
33 - sifive,fu540-c000-clint # SiFive FU540
34 - starfive,jh7100-clint # StarFive JH7100
35 - starfive,jh7110-clint # StarFive JH7110
36 - starfive,jh8100-clint # StarFive JH8100
37 - const: sifive,clint0 # SiFive CLINT v0 IP block
38 - items:
39 - enum:
40 - allwinner,sun20i-d1-clint
41 - sophgo,cv1800b-clint
42 - sophgo,cv1812h-clint
43 - thead,th1520-clint
44 - const: thead,c900-clint
45 - items:
46 - const: sifive,clint0
47 - const: riscv,clint0
52 Should be "<vendor>,<chip>-clint", followed by "sifive,clint<version>"
53 when compatible with a SiFive CLINT. Please refer to
54 sifive-blocks-ip-versioning.txt for details regarding the latter.
59 interrupts-extended:
66 - compatible
67 - reg
68 - interrupts-extended
71 - |
73 compatible = "sifive,fu540-c000-clint", "sifive,clint0";
74 interrupts-extended = <&cpu1intc 3>, <&cpu1intc 7>,