Lines Matching +full:single +full:- +full:trigger
1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/timer/nvidia,tegra-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stephen Warren <swarren@nvidia.com>
13 - if:
17 const: nvidia,tegra210-timer
21 # Either a single combined interrupt or up to 14 individual interrupts
27 - if:
31 - items:
32 - enum:
33 - nvidia,tegra114-timer
34 - nvidia,tegra124-timer
35 - nvidia,tegra132-timer
36 - const: nvidia,tegra30-timer
37 - items:
38 - const: nvidia,tegra30-timer
39 - const: nvidia,tegra20-timer
43 # Either a single combined interrupt or up to 6 individual interrupts
50 - if:
53 const: nvidia,tegra20-timer
57 # Either a single combined interrupt or up to 4 individual interrupts
66 - const: nvidia,tegra210-timer
68 The Tegra210 timer provides fourteen 29-bit timer counters and one 32-bit
70 from the oscillator clock (TMR0-TMR9) or directly at the oscillator clock
71 (TMR10-TMR13). Each TMR can be programmed to generate one-shot, periodic,
73 - items:
74 - enum:
75 - nvidia,tegra114-timer
76 - nvidia,tegra124-timer
77 - nvidia,tegra132-timer
78 - const: nvidia,tegra30-timer
79 - items:
80 - const: nvidia,tegra30-timer
81 - const: nvidia,tegra20-timer
83 The Tegra30 timer provides ten 29-bit timer channels, a single 32-bit free
85 trigger a legacy watchdog reset.
86 - const: nvidia,tegra20-timer
88 The Tegra20 timer provides four 29-bit timer channels and a single 32-bit free
89 running counter. The first two channels may also trigger a watchdog reset.
99 clock-names:
101 - const: timer
105 - compatible
106 - reg
107 - interrupts
108 - clocks
113 - |
114 #include <dt-bindings/interrupt-controller/irq.h>
116 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
126 - |
127 #include <dt-bindings/clock/tegra210-car.h>
128 #include <dt-bindings/interrupt-controller/arm-gic.h>
129 #include <dt-bindings/interrupt-controller/irq.h>
132 compatible = "nvidia,tegra210-timer";
149 clock-names = "timer";