Lines Matching +full:primary +full:- +full:pmic

1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/spmi/qcom,spmi-pmic-arb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SPMI Controller (PMIC Arbiter)
10   - Stephen Boyd <sboyd@kernel.org>
13   The SPMI PMIC Arbiter is found on Snapdragon chipsets. It is an SPMI
14   controller with wrapping arbitration logic to allow for multiple on-chip
17   The PMIC Arbiter can also act as an interrupt controller, providing interrupts
21   - $ref: spmi.yaml
25     const: qcom,spmi-pmic-arb
29       - items: # V1
30           - description: core registers
31           - description: interrupt controller registers
32           - description: configuration registers
33       - items: # V2
34           - description: core registers
35           - description: tx-channel per virtual slave regosters
36           - description: rx-channel (called observer) per virtual slave registers
37           - description: interrupt controller registers
38           - description: configuration registers
40   reg-names:
42       - items:
43           - const: core
44           - const: intr
45           - const: cnfg
46       - items:
47           - const: core
48           - const: chnls
49           - const: obsrvr
50           - const: intr
51           - const: cnfg
56   interrupt-names:
59   interrupt-controller: true
61   '#address-cells': true
63   '#interrupt-cells':
66       cell 1: slave ID for the requested interrupt (0-15)
67       cell 2: peripheral ID for requested interrupt (0-255)
68       cell 3: the requested peripheral interrupt (0-7)
69       cell 4: interrupt flags indicating level-sense information,
70               as defined in dt-bindings/interrupt-controller/irq.h
72   '#size-cells': true
86       which of the PMIC Arb provided channels to use for accesses
88   qcom,bus-id:
93       SPMI bus instance. only applicable to PMIC arbiter version 7 and beyond.
94       Supported values, 0 = primary bus, 1 = secondary bus
97   - compatible
98   - reg-names
99   - qcom,ee
100   - qcom,channel
105   - |
107         compatible = "qcom,spmi-pmic-arb";
108         reg-names = "core", "intr", "cnfg";
113         interrupt-names = "periph_irq";
119         #address-cells = <2>;
120         #size-cells = <0>;
122         interrupt-controller;
123         #interrupt-cells = <4>;
125         qcom,bus-id = <0>;