Lines Matching +full:spi +full:- +full:bus

3 ADI is the abbreviation of Anolog-Digital interface, which is used to access
4 analog chip (such as PMIC) from digital chip. ADI controller follows the SPI
5 framework for its hardware implementation is alike to SPI bus and its timing
6 is compatile to SPI timing.
16 Thus we introduce one property named "sprd,hw-channels" to configure hardware
21 Since we have multi-subsystems will use unique ADI to access analog chip, when
34 - compatible: Should be "sprd,sc9860-adi".
35 - reg: Offset and length of ADI-SPI controller register space.
36 - #address-cells: Number of cells required to define a chip select address
37 	on the ADI-SPI bus. Should be set to 1.
38 - #size-cells: Size of cells required to define a chip select address size
39 	on the ADI-SPI bus. Should be set to 0.
42 - hwlocks: Reference to a phandle of a hwlock provider node.
43 - hwlock-names: Reference to hwlock name strings defined in the same order
45 - sprd,hw-channels: This is an array of channel values up to 49 channels.
51 SPI slave nodes must be children of the SPI controller node and can contain
52 properties described in Documentation/devicetree/bindings/spi/spi-bus.txt.
55 	adi_bus: spi@40030000 {
56 		compatible = "sprd,sc9860-adi";
59 		hwlock-names = "adi";
60 		#address-cells = <1>;
61 		#size-cells = <0>;
62 		sprd,hw-channels = <30 0x8c20>;