Lines Matching +full:connect +full:- +full:gpios
4 Keystone 2 - https://www.ti.com/lit/ug/sprugp2a/sprugp2a.pdf
5 dm644x - https://www.ti.com/lit/ug/sprue32a/sprue32a.pdf
6 OMAP-L138/da830 - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
9 - #address-cells: number of cells required to define a chip select
11 - #size-cells: should be zero.
12 - compatible:
13 - "ti,dm6441-spi" for SPI used similar to that on DM644x SoC family
14 - "ti,da830-spi" for SPI used similar to that on DA8xx SoC family
15 - "ti,keystone-spi" for SPI used similar to that on Keystone2 SoC
17 - reg: Offset and length of SPI controller register space
18 - num-cs: Number of chip selects. This includes internal as well as
20 - ti,davinci-spi-intr-line: interrupt line used to connect the SPI
25 - interrupts: interrupt number mapped to CPU.
26 - clocks: spi clk phandle
28 Documentation/devicetree/bindings/clock/ti,sci-clk.yaml
30 SoC-specific Required Properties:
34 - power-domains: Should contain a phandle to a PM domain provider node
39 - cs-gpios: gpio chip selects
41 cs-gpios = <0>, <0>, <0>, <&gpio1 30 0>, <&gpio1 31 0>;
49 - ti,spi-wdelay : delay between transmission of words
56 "ti,spi-wdelay" parameter.
58 +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+
60 +----------+ +-+ +-+ +-+ +-+ +---------------------------+ +-+ +-+ +-
62 SPI_SOMI/SIMO+-----------------+ +-----------
63 +----------+ word1 +---------------------------+word2
64 +-----------------+ +-----------
66 <-------------------------->
72 #address-cells = <1>;
73 #size-cells = <0>;
74 compatible = "ti,dm6446-spi";
76 num-cs = <4>;
77 ti,davinci-spi-intr-line = <0>;
82 #address-cells = <1>;
83 #size-cells = <1>;
85 spi-max-frequency = <25000000>;
87 ti,spi-wdelay = <8>;
90 label = "u-boot-spl";
92 read-only;