Lines Matching +full:spdif +full:- +full:controller

1 Device-Tree bindings for Xilinx SPDIF IP
3 The IP supports playback and capture of SPDIF audio
6  - compatible: "xlnx,spdif-2.0"
7  - clock-names: List of input clocks.
9  - clocks: Input clock specifier. Refer to common clock bindings.
10  - reg: Base address and address length of the IP core instance.
11  - interrupts-parent: Phandle for interrupt controller.
12  - interrupts: List of Interrupt numbers.
13  - xlnx,spdif-mode: 0 :- receiver mode
14 		    1 :- transmitter mode
15  - xlnx,aud_clk_i: input audio clock value.
18 	spdif_0: spdif@80010000 {
19 		clock-names = "aud_clk_i", "s_axi_aclk";
21 		compatible = "xlnx,spdif-2.0";
22 		interrupt-names = "spdif_interrupt";
23 		interrupt-parent = <&gic>;
26 		xlnx,spdif-mode = <1>;