Lines Matching +full:tx1 +full:- +full:1

4 - compatible : For Tegra30, must contain "nvidia,tegra30-ahub".  For Tegra114,
5   must contain "nvidia,tegra114-ahub".  For Tegra124, must contain
6   "nvidia,tegra124-ahub".  Otherwise, must contain "nvidia,<chip>-ahub",
8 - reg : Should contain the register physical address and length for each of
10   - Tegra30 requires 2 entries, for the APBIF and AHUB/AUDIO register blocks.
11   - Tegra114 requires an additional entry, for the APBIF2 register block.
12 - interrupts : Should contain AHUB interrupt
13 - clocks : Must contain an entry for each entry in clock-names.
14   See ../clocks/clock-bindings.txt for details.
15 - clock-names : Must include the following entries:
16   - d_audio
17   - apbif
18 - resets : Must contain an entry for each entry in reset-names.
20 - reset-names : Must include the following entries:
22   - d_audio
23   - apbif
24   - i2s0
25   - i2s1
26   - i2s2
27   - i2s3
28   - i2s4
29   - dam0
30   - dam1
31   - dam2
32   - spdif
34   - amx
35   - adx
37   - amx1
38   - adx1
39   - afc0
40   - afc1
41   - afc2
42   - afc3
43   - afc4
44   - afc5
45 - ranges : The bus address mapping for the configlink register bus.
46   Can be empty since the mapping is 1:1.
47 - dmas : Must contain an entry for each entry in clock-names.
49 - dma-names : Must include the following entries:
50   - rx0 .. rx<n>
51   - tx0 .. tx<n>
55 - #address-cells : For the configlink bus. Should be <1>;
56 - #size-cells : For the configlink bus. Should be <1>.
60 register space (APBIF 0..3 RX, I2S 0..5 RX, DAM 0..2 RX 0..1, SPDIF RX 0..1).
62 registers (APBIF 0..3 TX, I2S 0..5 TX, DAM 0..2 TX, SPDIF TX 0..1).
67 	compatible = "nvidia,tegra30-ahub";
70 	nvidia,dma-request-selector = <&apbdma 1>;
72 	clock-names = "d_audio", "apbif";
77 	reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
80 	dmas = <&apbdma 1>, <&apbdma 1>;
84 	dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", "rx3", "tx3";
86 	#address-cells = <1>;
87 	#size-cells = <1>;