Lines Matching +full:tx1 +full:- +full:0
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra-audio-graph-card.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Jon Hunter <jonathanh@nvidia.com>
16 - Sameer Pujar <spujar@nvidia.com>
19 - $ref: audio-graph.yaml#
24 - nvidia,tegra210-audio-graph-card
25 - nvidia,tegra186-audio-graph-card
30 clock-names:
32 - const: pll_a
33 - const: plla_out0
35 assigned-clocks:
39 assigned-clock-parents:
43 assigned-clock-rates:
49 - description: APE read memory client
50 - description: APE write memory client
52 interconnect-names:
54 - const: dma-mem # read
55 - const: write
61 - clocks
62 - clock-names
63 - assigned-clocks
64 - assigned-clock-parents
69 - |
70 #include<dt-bindings/clock/tegra210-car.h>
73 compatible = "nvidia,tegra210-audio-graph-card";
77 clock-names = "pll_a", "plla_out0";
79 assigned-clocks = <&tegra_car TEGRA210_CLK_PLL_A>,
82 assigned-clock-parents = <0>, <0>, <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
83 assigned-clock-rates = <368640000>, <49152000>, <12288000>;
92 label = "jetson-tx1-ape";
97 compatible = "nvidia,tegra210-ahub";
98 reg = <0x702d0800 0x800>;
100 clock-names = "ahub";
101 assigned-clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
102 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
103 #address-cells = <1>;
104 #size-cells = <1>;
105 ranges = <0x702d0000 0x702d0000 0x0000e400>;
108 #address-cells = <1>;
109 #size-cells = <0>;
111 port@0 {
112 reg = <0x0>;
114 remote-endpoint = <&admaif1_ep>;
121 reg = <0xa>;
123 remote-endpoint = <&i2s1_cif_ep>;
129 compatible = "nvidia,tegra210-admaif";
130 reg = <0x702d0000 0x800>;
141 dma-names = "rx1", "tx1",
153 #address-cells = <1>;
154 #size-cells = <0>;
156 admaif1_port: port@0 {
157 reg = <0x0>;
159 remote-endpoint = <&xbar_admaif1_ep>;
168 compatible = "nvidia,tegra210-i2s";
170 clock-names = "i2s";
171 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S0>;
172 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
173 assigned-clock-rates = <1536000>;
174 reg = <0x702d1000 0x100>;
177 #address-cells = <1>;
178 #size-cells = <0>;
180 port@0 {
181 reg = <0x0>;
184 remote-endpoint = <&xbar_i2s1_ep>;
189 reg = <0x1>;
192 dai-format = "i2s";