Lines Matching +full:mt7622 +full:- +full:audsys
4 - compatible: should be one of the following.
5 - "mediatek,mt2701-audio"
6 - "mediatek,mt7622-audio"
7 - interrupts: should contain AFE and ASYS interrupts
8 - interrupt-names: should be "afe" and "asys"
9 - power-domains: should define the power domain
10 - clocks: Must contain an entry for each entry in clock-names
11 See ../clocks/clock-bindings.txt for details
12 - clock-names: should have these clock names:
47 - assigned-clocks: list of input clocks and dividers for the audio system.
48 See ../clocks/clock-bindings.txt for details.
49 - assigned-clocks-parents: parent of input clocks of assigned clocks.
50 - assigned-clock-rates: list of clock frequencies of assigned clocks.
52 Must be a subnode of MediaTek audsys device tree node.
53 See ../arm/mediatek/mediatek,audsys.txt for details about the parent node.
57 audsys: audio-subsystem@11220000 {
58 compatible = "mediatek,mt2701-audsys", "syscon";
61 afe: audio-controller {
62 compatible = "mediatek,mt2701-audio";
65 interrupt-names = "afe", "asys";
66 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
85 <&audsys CLK_AUD_I2SO1>,
86 <&audsys CLK_AUD_I2SO2>,
87 <&audsys CLK_AUD_I2SO3>,
88 <&audsys CLK_AUD_I2SO4>,
89 <&audsys CLK_AUD_I2SIN1>,
90 <&audsys CLK_AUD_I2SIN2>,
91 <&audsys CLK_AUD_I2SIN3>,
92 <&audsys CLK_AUD_I2SIN4>,
93 <&audsys CLK_AUD_ASRCO1>,
94 <&audsys CLK_AUD_ASRCO2>,
95 <&audsys CLK_AUD_ASRCO3>,
96 <&audsys CLK_AUD_ASRCO4>,
97 <&audsys CLK_AUD_AFE>,
98 <&audsys CLK_AUD_AFE_CONN>,
99 <&audsys CLK_AUD_A1SYS>,
100 <&audsys CLK_AUD_A2SYS>,
101 <&audsys CLK_AUD_AFE_MRGIF>;
103 clock-names = "infra_sys_audio_clk",
138 assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
142 assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
144 assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;