Lines Matching +full:tx +full:- +full:sync +full:- +full:clock

10   - compatible		: Compatible list, contains "fsl,vf610-sai",
11 			  "fsl,imx6sx-sai", "fsl,imx6ul-sai",
12 			  "fsl,imx7ulp-sai", "fsl,imx8mq-sai",
13 			  "fsl,imx8qm-sai", "fsl,imx8mm-sai",
14 			  "fsl,imx8mn-sai", "fsl,imx8mp-sai", or
15 			  "fsl,imx8ulp-sai".
17   - reg			: Offset and length of the register set for the device.
19   - clocks		: Must contain an entry for each entry in clock-names.
21   - clock-names		: Must include the "bus" for register access and
22 			  "mclk1", "mclk2", "mclk3" for bit clock and frame
23 			  clock providing.
24                           "pll8k", "pll11k" are optional, they are the clock
25                           source for root clock, one is for 8kHz series rates
27   - dmas		: Generic dma devicetree binding as described in
30   - dma-names		: Two dmas have to be defined, "tx" and "rx".
32   - pinctrl-names	: Must contain a "default" entry.
34   - pinctrl-NNN		: One property must exist for each entry in
35 			  pinctrl-names. See ../pinctrl/pinctrl-bindings.txt
38   - lsb-first		: Configures whether the LSB or the MSB is transmitted
43   - fsl,sai-synchronous-rx: This is a boolean property. If present, indicating
44 			  that SAI will work in the synchronous mode (sync Tx
47 			  receiver's bit clocks and frame sync clocks.
49   - fsl,sai-asynchronous: This is a boolean property. If present, indicating
53 			  frame sync clocks separately.
55   - fsl,dataline        : configure the dataline. it has 3 value for each configuration
58                           third one is dataline mask for 'tx'.
60                           it means I2S type rx mask is 0xff, tx mask is 0xff, PDM type
61                           rx mask is 0xff, tx mask is 0x11 (dataline 1 and 4 enabled).
65   - big-endian		: Boolean property, required if all the SAI
66 			  registers are big-endian rather than little-endian.
70   - fsl,sai-mclk-direction-output: This is a boolean property. If present,
71 			 indicates that SAI will output the SAI MCLK clock.
74 - If both fsl,sai-asynchronous and fsl,sai-synchronous-rx are absent, the
75   default synchronous mode (sync Rx with Tx) will be used, which means both
78 - fsl,sai-asynchronous and fsl,sai-synchronous-rx are exclusive.
82 	      compatible = "fsl,vf610-sai";
84 	      pinctrl-names = "default";
85 	      pinctrl-0 = <&pinctrl_sai2_1>;
89 	      clock-names = "bus", "mclk1", "mclk2", "mclk3";
90 	      dma-names = "tx", "rx";
93 	      big-endian;
94 	      lsb-first;