Lines Matching +full:big +full:- +full:endian
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shengjiu Wang <shengjiu.wang@nxp.com>
20 - fsl,imx35-spdif
21 - fsl,vf610-spdif
22 - fsl,imx6sx-spdif
23 - fsl,imx8qm-spdif
24 - fsl,imx8qxp-spdif
25 - fsl,imx8mq-spdif
26 - fsl,imx8mm-spdif
27 - fsl,imx8mn-spdif
28 - fsl,imx8ulp-spdif
36 - description: Combined or receive interrupt
37 - description: Transmit interrupt
41 - description: DMA controller phandle and request line for RX
42 - description: DMA controller phandle and request line for TX
44 dma-names:
46 - const: rx
47 - const: tx
51 - description: The core clock of spdif controller.
52 - description: Clock for tx0 and rx0.
53 - description: Clock for tx1 and rx1.
54 - description: Clock for tx2 and rx2.
55 - description: Clock for tx3 and rx3.
56 - description: Clock for tx4 and rx4.
57 - description: Clock for tx5 and rx5.
58 - description: Clock for tx6 and rx6.
59 - description: Clock for tx7 and rx7.
60 - description: The spba clock is required when SPDIF is placed as a bus
64 - description: PLL clock source for 8kHz series rate, optional.
65 - description: PLL clock source for 11khz series rate, optional.
68 clock-names:
70 - const: core
71 - const: rxtx0
72 - const: rxtx1
73 - const: rxtx2
74 - const: rxtx3
75 - const: rxtx4
76 - const: rxtx5
77 - const: rxtx6
78 - const: rxtx7
79 - const: spba
80 - const: pll8k
81 - const: pll11k
84 big-endian:
87 If this property is absent, the native endian mode will be in use
88 as default, or the big endian mode will be in use for all the device
89 registers. Set this flag for HCDs with big endian descriptors and big
90 endian registers.
92 power-domains:
96 - compatible
97 - reg
98 - interrupts
99 - dmas
100 - dma-names
101 - clocks
102 - clock-names
107 - if:
111 - fsl,imx8qm-spdif
112 - fsl,imx8qxp-spdif
122 - if:
127 - fsl,imx8qm-spdif
128 - fsl,imx8qxp-spdif
131 - power-domains
134 - |
136 compatible = "fsl,imx35-spdif";
141 dma-names = "rx", "tx";
147 clock-names = "core", "rxtx0",
152 big-endian;