Lines Matching +full:rk3588 +full:- +full:cru
1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
15 - items:
16 - enum:
17 - rockchip,rk3288-sgrf
18 - rockchip,rk3566-pipe-grf
19 - rockchip,rk3568-pcie3-phy-grf
20 - rockchip,rk3568-pipe-grf
21 - rockchip,rk3568-pipe-phy-grf
22 - rockchip,rk3568-usb2phy-grf
23 - rockchip,rk3588-bigcore0-grf
24 - rockchip,rk3588-bigcore1-grf
25 - rockchip,rk3588-ioc
26 - rockchip,rk3588-php-grf
27 - rockchip,rk3588-pipe-phy-grf
28 - rockchip,rk3588-sys-grf
29 - rockchip,rk3588-pcie3-phy-grf
30 - rockchip,rk3588-pcie3-pipe-grf
31 - rockchip,rk3588-vo-grf
32 - rockchip,rk3588-vop-grf
33 - rockchip,rv1108-usbgrf
34 - const: syscon
35 - items:
36 - enum:
37 - rockchip,px30-grf
38 - rockchip,px30-pmugrf
39 - rockchip,px30-usb2phy-grf
40 - rockchip,rk3036-grf
41 - rockchip,rk3066-grf
42 - rockchip,rk3128-grf
43 - rockchip,rk3188-grf
44 - rockchip,rk3228-grf
45 - rockchip,rk3288-grf
46 - rockchip,rk3308-core-grf
47 - rockchip,rk3308-detect-grf
48 - rockchip,rk3308-grf
49 - rockchip,rk3308-usb2phy-grf
50 - rockchip,rk3328-grf
51 - rockchip,rk3328-usb2phy-grf
52 - rockchip,rk3368-grf
53 - rockchip,rk3368-pmugrf
54 - rockchip,rk3399-grf
55 - rockchip,rk3399-pmugrf
56 - rockchip,rk3568-grf
57 - rockchip,rk3568-pmugrf
58 - rockchip,rk3588-usb2phy-grf
59 - rockchip,rv1108-grf
60 - rockchip,rv1108-pmugrf
61 - rockchip,rv1126-grf
62 - rockchip,rv1126-pmugrf
63 - const: syscon
64 - const: simple-mfd
69 "#address-cells":
72 "#size-cells":
76 - compatible
77 - reg
83 - if:
88 - rockchip,px30-grf
99 - if:
103 const: rockchip,rk3288-grf
107 edp-phy:
109 $ref: /schemas/phy/rockchip,rk3288-dp-phy.yaml#
112 - if:
117 - rockchip,rk3066-grf
118 - rockchip,rk3188-grf
119 - rockchip,rk3288-grf
126 $ref: /schemas/phy/rockchip-usb-phy.yaml#
130 - if:
134 const: rockchip,rk3328-grf
141 $ref: /schemas/gpio/rockchip,rk3328-grf-gpio.yaml#
145 power-controller:
148 $ref: /schemas/power/rockchip,power-controller.yaml#
152 - if:
156 const: rockchip,rk3399-grf
160 mipi-dphy-rx0:
163 $ref: /schemas/phy/rockchip-mipi-dphy-rx0.yaml#
167 pcie-phy:
169 Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
172 "phy@[0-9a-f]+$":
174 Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt
176 - if:
181 - rockchip,px30-pmugrf
182 - rockchip,rk3036-grf
183 - rockchip,rk3308-grf
184 - rockchip,rk3368-pmugrf
188 reboot-mode:
191 $ref: /schemas/power/reset/syscon-reboot-mode.yaml#
195 - if:
200 - rockchip,px30-usb2phy-grf
201 - rockchip,rk3128-grf
202 - rockchip,rk3228-grf
203 - rockchip,rk3308-usb2phy-grf
204 - rockchip,rk3328-usb2phy-grf
205 - rockchip,rk3399-grf
206 - rockchip,rk3588-usb2phy-grf
207 - rockchip,rv1108-grf
211 - "#address-cells"
212 - "#size-cells"
215 "usb2phy@[0-9a-f]+$":
218 $ref: /schemas/phy/rockchip,inno-usb2phy.yaml#
222 - if:
227 - rockchip,px30-grf
228 - rockchip,px30-pmugrf
229 - rockchip,rk3188-grf
230 - rockchip,rk3228-grf
231 - rockchip,rk3288-grf
232 - rockchip,rk3328-grf
233 - rockchip,rk3368-grf
234 - rockchip,rk3368-pmugrf
235 - rockchip,rk3399-grf
236 - rockchip,rk3399-pmugrf
237 - rockchip,rk3568-pmugrf
238 - rockchip,rk3588-pmugrf
239 - rockchip,rv1108-grf
240 - rockchip,rv1108-pmugrf
244 io-domains:
247 $ref: /schemas/power/rockchip-io-domain.yaml#
252 - |
253 #include <dt-bindings/clock/rk3399-cru.h>
254 #include <dt-bindings/interrupt-controller/arm-gic.h>
255 #include <dt-bindings/power/rk3399-power.h>
257 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
259 #address-cells = <1>;
260 #size-cells = <1>;
262 mipi_dphy_rx0: mipi-dphy-rx0 {
263 compatible = "rockchip,rk3399-mipi-dphy-rx0";
264 clocks = <&cru SCLK_MIPIDPHY_REF>,
265 <&cru SCLK_DPHY_RX0_CFG>,
266 <&cru PCLK_VIO_GRF>;
267 clock-names = "dphy-ref", "dphy-cfg", "grf";
268 power-domains = <&power RK3399_PD_VIO>;
269 #phy-cells = <0>;
273 compatible = "rockchip,rk3399-usb2phy";
275 clocks = <&cru SCLK_USB2PHY0_REF>;
276 clock-names = "phyclk";
277 #clock-cells = <0>;
278 clock-output-names = "clk_usbphy0_480m";
280 u2phy0_host: host-port {
281 #phy-cells = <0>;
283 interrupt-names = "linestate";
286 u2phy0_otg: otg-port {
287 #phy-cells = <0>;
291 interrupt-names = "otg-bvalid", "otg-id",