Lines Matching +full:dt +full:- +full:node
1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andy Gross <agross@kernel.org>
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
12 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
15 The GSBI controller is modeled as a node with zero or more child nodes, each
16 representing a serial sub-node device that is mux'd as part of the GSBI
20 A GSBI controller node can contain 0 or more child nodes representing serial
26 const: qcom,gsbi-v1.0.0
28 '#address-cells':
31 cell-index:
39 clock-names:
46 include/dt-bindings/soc/qcom,gsbi.h for valid CRCI mux values.
52 include/dt-bindings/soc/qcom,gsbi.h for valid mux values.
54 '#size-cells':
57 syscon-tcsr:
60 Phandle of TCSR syscon node.Required if child uses dma.
68 "spi@[0-9a-f]+$":
70 $ref: /schemas/spi/qcom,spi-qup.yaml#
72 "i2c@[0-9a-f]+$":
74 $ref: /schemas/i2c/qcom,i2c-qup.yaml#
76 "serial@[0-9a-f]+$":
78 $ref: /schemas/serial/qcom,msm-uartdm.yaml#
81 - compatible
82 - cell-index
83 - clocks
84 - clock-names
85 - qcom,mode
86 - reg
91 - |
92 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
93 #include <dt-bindings/interrupt-controller/arm-gic.h>
94 #include <dt-bindings/soc/qcom,gsbi.h>
97 compatible = "qcom,gsbi-v1.0.0";
99 cell-index = <1>;
101 clock-names = "iface";
102 #address-cells = <1>;
103 #size-cells = <1>;
106 syscon-tcsr = <&tcsr>;
110 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
115 clock-names = "core", "iface";
119 compatible = "qcom,i2c-qup-v1.1.1";
121 pinctrl-0 = <&i2c1_pins>;
122 pinctrl-1 = <&i2c1_pins_sleep>;
123 pinctrl-names = "default", "sleep";
126 clock-names = "core", "iface";
127 #address-cells = <1>;
128 #size-cells = <0>;