Lines Matching +full:cache +full:- +full:controller +full:- +full:0

1 SiFive L2 Cache Controller
2 --------------------------
3 The SiFive Level 2 Cache Controller is used to provide access to fast copies
4 of memory for masters in a Core Complex. The Level 2 Cache Controller also
5 acts as directory-based coherency manager.
9 --------------------
10 - compatible: Should be "sifive,fu540-c000-ccache" and "cache"
12 - cache-block-size: Specifies the block size in bytes of the cache.
15 - cache-level: Should be set to 2 for a level 2 cache
17 - cache-sets: Specifies the number of associativity sets of the cache.
20 - cache-size: Specifies the size in bytes of the cache. Should be 2097152
22 - cache-unified: Specifies the cache is a unified cache
24 - interrupts: Must contain 3 entries (DirError, DataError and DataFail signals)
26 - reg: Physical base address and size of L2 cache controller registers map
29 --------------------
30 - next-level-cache: phandle to the next level cache if present.
32 - memory-region: reference to the reserved-memory for the L2 Loosely Integrated
34   in reserved-memory.txt
39 	cache-controller@2010000 {
40 		compatible = "sifive,fu540-c000-ccache", "cache";
41 		cache-block-size = <64>;
42 		cache-level = <2>;
43 		cache-sets = <1024>;
44 		cache-size = <2097152>;
45 		cache-unified;
46 		interrupt-parent = <&plic0>;
48 		reg = <0x0 0x2010000 0x0 0x1000>;
49 		next-level-cache = <&L25 &L40 &L36>;
50 		memory-region = <&l2_lim>;