Lines Matching +full:cache +full:- +full:controller +full:- +full:0

1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive Composable Cache Controller
11   - Paul Walmsley <paul.walmsley@sifive.com>
14   The SiFive Composable Cache Controller is used to provide access to fast copies
15   of memory for masters in a Core Complex. The Composable Cache Controller also
16   acts as directory-based coherency manager.
24           - sifive,ccache0
25           - sifive,fu540-c000-ccache
26           - sifive,fu740-c000-ccache
29     - compatible
34       - items:
35           - enum:
36               - sifive,ccache0
37               - sifive,fu540-c000-ccache
38               - sifive,fu740-c000-ccache
39           - const: cache
40       - items:
41           - const: starfive,jh7110-ccache
42           - const: sifive,ccache0
43           - const: cache
44       - items:
45           - const: microchip,mpfs-ccache
46           - const: sifive,fu540-c000-ccache
47           - const: cache
49   cache-block-size:
52   cache-level:
55   cache-sets:
58   cache-size:
61   cache-unified: true
66       - description: DirError interrupt
67       - description: DataError interrupt
68       - description: DataFail interrupt
69       - description: DirFail interrupt
74   next-level-cache: true
76   memory-region:
79       The reference to the reserved-memory for the L2 Loosely Integrated Memory region.
80       The reserved memory node should be defined as per the bindings in reserved-memory.txt.
83   - $ref: /schemas/cache-controller.yaml#
85   - if:
90               - sifive,fu740-c000-ccache
91               - starfive,jh7110-ccache
92               - microchip,mpfs-ccache
108   - if:
113               - sifive,fu740-c000-ccache
114               - starfive,jh7110-ccache
118         cache-sets:
123         cache-sets:
126   - if:
134         cache-level:
139         cache-level:
145   - compatible
146   - cache-block-size
147   - cache-level
148   - cache-sets
149   - cache-size
150   - cache-unified
151   - interrupts
152   - reg
155   - |
156     cache-controller@2010000 {
157         compatible = "sifive,fu540-c000-ccache", "cache";
158         cache-block-size = <64>;
159         cache-level = <2>;
160         cache-sets = <1024>;
161         cache-size = <2097152>;
162         cache-unified;
163         reg = <0x2010000 0x1000>;
164         interrupt-parent = <&plic0>;
168         next-level-cache = <&L25>;
169         memory-region = <&l2_lim>;