Lines Matching +full:cache +full:- +full:controller +full:- +full:0
1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V CPUs
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 This document uses some terminology common to the RISC-V community
19 mandated by the RISC-V ISA: a PC and some registers. This
27 - $ref: /schemas/cpu.yaml#
28 - $ref: extensions.yaml
33 - items:
34 - enum:
35 - amd,mbv32
36 - andestech,ax45mp
37 - canaan,k210
38 - sifive,bullet0
39 - sifive,e5
40 - sifive,e7
41 - sifive,e71
42 - sifive,rocket0
43 - sifive,s7
44 - sifive,u5
45 - sifive,u54
46 - sifive,u7
47 - sifive,u74
48 - sifive,u74-mc
49 - thead,c906
50 - thead,c910
51 - thead,c920
52 - const: riscv
53 - items:
54 - enum:
55 - sifive,e51
56 - sifive,u54-mc
57 - const: sifive,rocket0
58 - const: riscv
59 - const: riscv # Simulator only
61 Identifies that the hart uses the RISC-V instruction set
64 mmu-type:
67 this hart. These values originate from the RISC-V Privileged
72 - riscv,sv32
73 - riscv,sv39
74 - riscv,sv48
75 - riscv,sv57
76 - riscv,none
78 riscv,cbom-block-size:
81 The blocksize in bytes for the Zicbom cache operations.
83 riscv,cbop-block-size:
86 The blocksize in bytes for the Zicbop cache operations.
88 riscv,cboz-block-size:
91 The blocksize in bytes for the Zicboz cache operations.
93 # RISC-V has multiple properties for cache op block sizes as the sizes
95 cache-op-block-size: false
96 # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
97 timebase-frequency: false
99 interrupt-controller:
102 description: Describes the CPU's local interrupt controller
105 '#interrupt-cells':
109 const: riscv,cpu-intc
111 interrupt-controller: true
114 - '#interrupt-cells'
115 - compatible
116 - interrupt-controller
118 cpu-idle-states:
119 $ref: /schemas/types.yaml#/definitions/phandle-array
124 by this hart (see ./idle-states.yaml).
126 capacity-dmips-mhz:
128 u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in
129 DMIPS/MHz, relative to highest capacity-dmips-mhz
133 - required:
134 - riscv,isa
135 - required:
136 - riscv,isa-base
139 riscv,isa-base: [ "riscv,isa-extensions" ]
140 riscv,isa-extensions: [ "riscv,isa-base" ]
143 - interrupt-controller
148 - |
151 #address-cells = <1>;
152 #size-cells = <0>;
153 timebase-frequency = <1000000>;
154 cpu@0 {
155 clock-frequency = <0>;
158 i-cache-block-size = <64>;
159 i-cache-sets = <128>;
160 i-cache-size = <16384>;
161 reg = <0>;
162 riscv,isa-base = "rv64i";
163 riscv,isa-extensions = "i", "m", "a", "c";
165 cpu_intc0: interrupt-controller {
166 #interrupt-cells = <1>;
167 compatible = "riscv,cpu-intc";
168 interrupt-controller;
172 clock-frequency = <0>;
174 d-cache-block-size = <64>;
175 d-cache-sets = <64>;
176 d-cache-size = <32768>;
177 d-tlb-sets = <1>;
178 d-tlb-size = <32>;
180 i-cache-block-size = <64>;
181 i-cache-sets = <64>;
182 i-cache-size = <32768>;
183 i-tlb-sets = <1>;
184 i-tlb-size = <32>;
185 mmu-type = "riscv,sv39";
187 tlb-split;
188 riscv,isa-base = "rv64i";
189 riscv,isa-extensions = "i", "m", "a", "f", "d", "c";
191 cpu_intc1: interrupt-controller {
192 #interrupt-cells = <1>;
193 compatible = "riscv,cpu-intc";
194 interrupt-controller;
199 - |
202 #address-cells = <1>;
203 #size-cells = <0>;
204 cpu@0 {
206 reg = <0>;
208 mmu-type = "riscv,sv48";
209 riscv,isa-base = "rv64i";
210 riscv,isa-extensions = "i", "m", "a", "f", "d", "c";
212 interrupt-controller {
213 #interrupt-cells = <1>;
214 interrupt-controller;
215 compatible = "riscv,cpu-intc";