Lines Matching +full:zynqmp +full:- +full:power
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/xlnx,zynqmp-r5fss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ben Levinsky <ben.levinsky@amd.com>
11 - Tanmay Shah <tanmay.shah@amd.com>
14 The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for
15 real-time processing based on the Cortex-R5F processor core from ARM.
16 The Cortex-R5F processor implements the Arm v7-R architecture and includes a
17 floating-point unit that implements the Arm VFPv3 instruction set.
21 const: xlnx,zynqmp-r5fss
23 xlnx,cluster-mode:
27 The RPU MPCore can operate in split mode (Dual-processor performance), Safety
28 lock-step mode(Both RPU cores execute the same code in lock-step,
29 clock-for-clock) or Single CPU mode (RPU core 0 is held in reset while
40 "^r5f-[a-f0-9]+$":
43 The RPU is located in the Low Power Domain of the Processor Subsystem.
46 memory space is non-cacheable.
50 per processor. In lock-step mode, the processor has access to 256KB of
55 const: xlnx,zynqmp-r5f
57 power-domains:
63 - description: mailbox channel to send data to RPU
64 - description: mailbox channel to receive data from RPU
66 mbox-names:
69 - const: tx
70 - const: rx
73 $ref: /schemas/types.yaml#/definitions/phandle-array
79 phandles to one or more reserved on-chip SRAM regions. Other than TCM,
87 memory-region:
96 - description: region used for RPU firmware image section
97 - description: vdev buffer
98 - description: vring0
99 - description: vring1
103 - compatible
104 - power-domains
109 - compatible
114 - |
116 compatible = "xlnx,zynqmp-r5fss";
117 xlnx,cluster-mode = <1>;
119 r5f-0 {
120 compatible = "xlnx,zynqmp-r5f";
121 power-domains = <&zynqmp_firmware 0x7>;
122 memory-region = <&rproc_0_fw_image>, <&rpu0vdev0buffer>, <&rpu0vdev0vring0>, <&rpu0vdev0vring1>;
124 mbox-names = "tx", "rx";
127 r5f-1 {
128 compatible = "xlnx,zynqmp-r5f";
129 power-domains = <&zynqmp_firmware 0x8>;
130 memory-region = <&rproc_1_fw_image>, <&rpu1vdev0buffer>, <&rpu1vdev0vring0>, <&rpu1vdev0vring1>;
132 mbox-names = "tx", "rx";