Lines Matching +full:0 +full:xffeb0000
39 enum: [0, 1, 2]
44 clock-for-clock) or Single CPU mode (RPU core 0 is held in reset while
47 If set to 1 then lockstep mode and if 0 then split mode.
50 0: split mode
56 enum: [0, 1]
59 0: split mode
63 "^r(.*)@[0-9a-f]+$":
162 "^r52f@[0-9a-f]+$":
206 "^r5f@[0-9a-f]+$":
241 enum: [0]
244 "^r5f@[0-9a-f]+$":
283 xlnx,cluster-mode = <0>;
284 xlnx,tcm-mode = <0>;
288 ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x10000>,
289 <0x0 0x20000 0x0 0xffe20000 0x0 0x10000>,
290 <0x1 0x0 0x0 0xffe90000 0x0 0x10000>,
291 <0x1 0x20000 0x0 0xffeb0000 0x0 0x10000>;
293 r5f@0 {
295 reg = <0x0 0x0 0x0 0x10000>, <0x0 0x20000 0x0 0x10000>;
302 mboxes = <&ipi_mailbox_rpu0 0>, <&ipi_mailbox_rpu0 1>;
308 reg = <0x1 0x0 0x0 0x10000>, <0x1 0x20000 0x0 0x10000>;
315 mboxes = <&ipi_mailbox_rpu1 0>, <&ipi_mailbox_rpu1 1>;
334 ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x10000>,
335 <0x0 0x20000 0x0 0xffe20000 0x0 0x10000>,
336 <0x0 0x10000 0x0 0xffe10000 0x0 0x10000>,
337 <0x0 0x30000 0x0 0xffe30000 0x0 0x10000>;
339 r5f@0 {
341 reg = <0x0 0x0 0x0 0x10000>,
342 <0x0 0x20000 0x0 0x10000>,
343 <0x0 0x10000 0x0 0x10000>,
344 <0x0 0x30000 0x0 0x10000>;
353 mboxes = <&ipi_mailbox_rpu0 0>, <&ipi_mailbox_rpu0 1>;
359 reg = <0x1 0x0 0x0 0x10000>, <0x1 0x20000 0x0 0x10000>;
366 mboxes = <&ipi_mailbox_rpu1 0>, <&ipi_mailbox_rpu1 1>;