Lines Matching +full:sdm845 +full:- +full:lpasscc
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,sdm845-adsp-pil.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SDM845 ADSP Peripheral Image Loader
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
19 - qcom,sdm845-adsp-pil
28 - description: Watchdog interrupt
29 - description: Fatal interrupt
30 - description: Ready interrupt
31 - description: Handover interrupt
32 - description: Stop acknowledge interrupt
34 interrupt-names:
36 - const: wdog
37 - const: fatal
38 - const: ready
39 - const: handover
40 - const: stop-ack
44 - description: XO clock
45 - description: SWAY clock
46 - description: LPASS AHBS AON clock
47 - description: LPASS AHBM AON clock
48 - description: QDSP XO clock
49 - description: Q6SP6SS SLEEP clock
50 - description: Q6SP6SS CORE clock
52 clock-names:
54 - const: xo
55 - const: sway_cbcr
56 - const: lpass_ahbs_aon_cbcr
57 - const: lpass_ahbm_aon_cbcr
58 - const: qdsp6ss_xo
59 - const: qdsp6ss_sleep
60 - const: qdsp6ss_core
62 power-domains:
64 - description: CX power domain
68 - description: PDC AUDIO SYNC RESET
69 - description: CC LPASS restart
71 reset-names:
73 - const: pdc_sync
74 - const: cc_lpass
76 memory-region:
78 description: Reference to the reserved-memory for the Hexagon core
80 qcom,halt-regs:
81 $ref: /schemas/types.yaml#/definitions/phandle-array
86 qcom,smem-states:
87 $ref: /schemas/types.yaml#/definitions/phandle-array
90 - description: Stop the modem
92 qcom,smem-state-names:
95 - const: stop
98 - compatible
99 - reg
100 - interrupts
101 - interrupt-names
102 - clocks
103 - clock-names
104 - power-domains
105 - resets
106 - reset-names
107 - qcom,halt-regs
108 - memory-region
109 - qcom,smem-states
110 - qcom,smem-state-names
115 - |
116 #include <dt-bindings/interrupt-controller/arm-gic.h>
117 #include <dt-bindings/clock/qcom,rpmh.h>
118 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
119 #include <dt-bindings/clock/qcom,lpass-sdm845.h>
120 #include <dt-bindings/power/qcom-rpmpd.h>
121 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
122 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
124 compatible = "qcom,sdm845-adsp-pil";
127 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
132 interrupt-names = "wdog", "fatal", "ready",
133 "handover", "stop-ack";
137 <&lpasscc LPASS_Q6SS_AHBS_AON_CLK>,
138 <&lpasscc LPASS_Q6SS_AHBM_AON_CLK>,
139 <&lpasscc LPASS_QDSP6SS_XO_CLK>,
140 <&lpasscc LPASS_QDSP6SS_SLEEP_CLK>,
141 <&lpasscc LPASS_QDSP6SS_CORE_CLK>;
142 clock-names = "xo", "sway_cbcr",
147 power-domains = <&rpmhpd SDM845_CX>;
151 reset-names = "pdc_sync", "cc_lpass";
153 qcom,halt-regs = <&tcsr_mutex_regs 0x22000>;
155 memory-region = <&pil_adsp_mem>;
157 qcom,smem-states = <&adsp_smp2p_out 0>;
158 qcom,smem-state-names = "stop";