Lines Matching full:description

12 description:
23       - description: MSS QDSP6 registers
24       - description: RMB registers
33       - description: MSA Stream 1
34       - description: MSA Stream 2
38       - description: Path leading to system memory
42       - description: Watchdog interrupt
43       - description: Fatal interrupt
44       - description: Ready interrupt
45       - description: Handover interrupt
46       - description: Stop acknowledge interrupt
47       - description: Shutdown acknowledge interrupt
60       - description: GCC MSS IFACE clock
61       - description: GCC MSS OFFLINE clock
62       - description: GCC MSS SNOC_AXI clock
63       - description: RPMH PKA clock
64       - description: RPMH XO clock
76       - description: CX power domain
77       - description: MSS power domain
86       - description: AOSS restart
87       - description: PDC reset
96       - description: MBA reserved region
97       - description: modem reserved region
98       - description: metadata reserved region
103       - description: Name of MBA firmware
104       - description: Name of modem firmware
108     description:
113           - description: phandle to TCSR_MUTEX registers
114           - description: offset to the Q6 halt register
115           - description: offset to the modem halt register
116           - description: offset to the nc halt register
117           - description: offset to the vq6 halt register
121     description: EXT registers are used for various power related functionality
124           - description: phandle to TCSR_REG registers
125           - description: offset to the force_clk_en register
126           - description: offset to the rscc_disable register
128           - description: phandle to TCSR_MUTEX registers
129           - description: offset to the axim1_clk_off register
130           - description: offset to the crypto_clk_off register
134     description: QACCEPT registers are used to bring up/down Q-channels
137           - description: phandle to TCSR_MUTEX registers
138           - description: offset to the mdm qaccept register
139           - description: offset to the cx qaccept register
140           - description: offset to the axi qaccept register
144     description: Reference to the AOSS side-channel message RAM.
148     description: States used by the AP to signal the Hexagon core
150       - description: Stop the modem
153     description: The names of the state bits used for SMP2P output
159     description:
166           - description: IRQ from MSS to GLINK
170           - description: Mailbox for communication between APPS and MSS