Lines Matching +full:8 +full:- +full:xo +full:- +full:supply
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,msm8996-mss-pil.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Sibi Sankar <quic_sibis@quicinc.com>
20 - qcom,msm8996-mss-pil
21 - qcom,msm8998-mss-pil
22 - qcom,sdm660-mss-pil
23 - qcom,sdm845-mss-pil
27 - description: MSS QDSP6 registers
28 - description: RMB registers
30 reg-names:
32 - const: qdsp6
33 - const: rmb
37 - description: MSA Stream 1
38 - description: MSA Stream 2
42 - description: Watchdog interrupt
43 - description: Fatal interrupt
44 - description: Ready interrupt
45 - description: Handover interrupt
46 - description: Stop acknowledge interrupt
47 - description: Shutdown acknowledge interrupt
49 interrupt-names:
51 - const: wdog
52 - const: fatal
53 - const: ready
54 - const: handover
55 - const: stop-ack
56 - const: shutdown-ack
59 minItems: 8
62 clock-names:
63 minItems: 8
66 power-domains:
68 - description: CX power domain
69 - description: MX power domain
70 - description: MSS power domain (only valid for qcom,sdm845-mss-pil)
73 power-domain-names:
75 - const: cx
76 - const: mx
77 - const: mss # only valid for qcom,sdm845-mss-pil
80 pll-supply:
81 description: PLL supply
85 - description: AOSS restart
86 - description: PDC reset (only valid for qcom,sdm845-mss-pil)
89 reset-names:
91 - const: mss_restart
92 - const: pdc_reset # only valid for qcom,sdm845-mss-pil
97 description: Reference to the AOSS side-channel message RAM.
99 qcom,smem-states:
100 $ref: /schemas/types.yaml#/definitions/phandle-array
103 - description: Stop modem
105 qcom,smem-state-names:
108 - const: stop
110 qcom,halt-regs:
111 $ref: /schemas/types.yaml#/definitions/phandle-array
113 Halt registers are used to halt transactions of various sub-components
116 - items:
117 - description: phandle to TCSR syscon region
118 - description: offset to the Q6 halt register
119 - description: offset to the modem halt register
120 - description: offset to the nc halt register
122 memory-region:
124 - description: MBA reserved region
125 - description: Modem reserved region
126 - description: Metadata reserved region
128 firmware-name:
129 $ref: /schemas/types.yaml#/definitions/string-array
131 - description: Name of MBA firmware
132 - description: Name of modem firmware
134 smd-edge:
135 $ref: /schemas/remoteproc/qcom,smd-edge.yaml#
141 glink-edge:
142 $ref: /schemas/remoteproc/qcom,glink-edge.yaml#
144 Qualcomm G-Link subnode which represents communication edge, channels
155 memory-region: true
158 - memory-region
169 memory-region: true
172 - memory-region
183 memory-region: true
186 - memory-region
192 - compatible
193 - reg
194 - reg-names
195 - interrupts
196 - interrupt-names
197 - clocks
198 - clock-names
199 - power-domains
200 - power-domain-names
201 - resets
202 - reset-names
203 - qcom,halt-regs
204 - qcom,smem-states
205 - qcom,smem-state-names
208 - if:
211 const: qcom,msm8996-mss-pil
216 - description: GCC MSS IFACE clock
217 - description: GCC MSS BUS clock
218 - description: GCC MSS MEM clock
219 - description: RPM XO clock
220 - description: GCC MSS GPLL0 clock
221 - description: GCC MSS SNOC_AXI clock
222 - description: GCC MSS MNOC_AXI clock
223 - description: RPM QDSS clock
224 clock-names:
226 - const: iface
227 - const: bus
228 - const: mem
229 - const: xo
230 - const: gpll0_mss
231 - const: snoc_axi
232 - const: mnoc_axi
233 - const: qdss
234 glink-edge: false
236 - pll-supply
237 - smd-edge
240 pll-supply: false
241 smd-edge: false
243 - if:
247 - qcom,msm8998-mss-pil
248 - qcom,sdm660-mss-pil
253 - description: GCC MSS IFACE clock
254 - description: GCC MSS BUS clock
255 - description: GCC MSS MEM clock
256 - description: GCC MSS GPLL0 clock
257 - description: GCC MSS SNOC_AXI clock
258 - description: GCC MSS MNOC_AXI clock
259 - description: RPMH QDSS clock
260 - description: RPMH XO clock
261 clock-names:
263 - const: iface
264 - const: bus
265 - const: mem
266 - const: gpll0_mss
267 - const: snoc_axi
268 - const: mnoc_axi
269 - const: qdss
270 - const: xo
272 - glink-edge
274 - if:
277 const: qcom,sdm845-mss-pil
280 power-domains:
282 power-domain-names:
286 reset-names:
290 - description: GCC MSS IFACE clock
291 - description: GCC MSS BUS clock
292 - description: GCC MSS MEM clock
293 - description: GCC MSS GPLL0 clock
294 - description: GCC MSS SNOC_AXI clock
295 - description: GCC MSS MNOC_AXI clock
296 - description: GCC MSS PRNG clock
297 - description: RPMH XO clock
298 clock-names:
300 - const: iface
301 - const: bus
302 - const: mem
303 - const: gpll0_mss
304 - const: snoc_axi
305 - const: mnoc_axi
306 - const: prng
307 - const: xo
309 - qcom,qmp
310 - glink-edge
314 power-domains:
316 power-domain-names:
320 reset-names:
325 - oneOf:
326 - required:
327 - memory-region
328 - required:
329 - mba
330 - mpss
331 - metadata
336 - |
337 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
338 #include <dt-bindings/clock/qcom,rpmh.h>
339 #include <dt-bindings/interrupt-controller/arm-gic.h>
340 #include <dt-bindings/power/qcom-rpmpd.h>
341 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
342 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
345 compatible = "qcom,sdm845-mss-pil";
347 reg-names = "qdsp6", "rmb";
349 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
355 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack",
356 "shutdown-ack";
366 clock-names = "iface", "bus", "mem", "gpll0_mss",
367 "snoc_axi", "mnoc_axi", "prng", "xo";
369 power-domains = <&rpmhpd SDM845_CX>,
372 power-domain-names = "cx", "mx", "mss";
374 memory-region = <&mba_mem>, <&mpss_mem>, <&mdata_mem>;
378 reset-names = "mss_restart", "pdc_reset";
380 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
384 qcom,smem-states = <&modem_smp2p_out 0>;
385 qcom,smem-state-names = "stop";
387 glink-edge {
390 qcom,remote-pid = <1>;