Lines Matching +full:sdm845 +full:- +full:lpasscc
6 - compatible:
10 "qcom,qcs404-cdsp-pil",
11 "qcom,sdm845-adsp-pil"
13 - reg:
15 Value type: <prop-encoded-array>
18 - interrupts-extended:
20 Value type: <prop-encoded-array>
22 stop-ack IRQs
24 - interrupt-names:
27 Definition: must be "wdog", "fatal", "ready", "handover", "stop-ack"
29 - clocks:
31 Value type: <prop-encoded-array>
33 per clock-names below.
35 - clock-names:
36 Usage: required for SDM845 ADSP
44 - clock-names:
52 - power-domains:
57 - resets:
62 - reset-names:
63 Usage: required for SDM845 ADSP
67 - reset-names:
72 - qcom,halt-regs:
74 Value type: <prop-encoded-array>
78 - memory-region:
81 Definition: reference to the reserved-memory for the firmware
83 - qcom,smem-states:
89 - qcom,smem-state-names:
96 The adsp node may have an subnode named "glink-edge" that describes the
102 ADSP, as it is found on SDM845 boards.
105 compatible = "qcom,sdm845-adsp-pil";
108 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
113 interrupt-names = "wdog", "fatal", "ready",
114 "handover", "stop-ack";
118 <&lpasscc LPASS_Q6SS_AHBS_AON_CLK>,
119 <&lpasscc LPASS_Q6SS_AHBM_AON_CLK>,
120 <&lpasscc LPASS_QDSP6SS_XO_CLK>,
121 <&lpasscc LPASS_QDSP6SS_SLEEP_CLK>,
122 <&lpasscc LPASS_QDSP6SS_CORE_CLK>;
123 clock-names = "xo", "sway_cbcr",
128 power-domains = <&rpmhpd SDM845_CX>;
132 reset-names = "pdc_sync", "cc_lpass";
134 qcom,halt-regs = <&tcsr_mutex_regs 0x22000>;
136 memory-region = <&pil_adsp_mem>;
138 qcom,smem-states = <&adsp_smp2p_out 0>;
139 qcom,smem-state-names = "stop";