Lines Matching +full:pwm +full:- +full:clock
1 MediaTek display PWM controller
4 - compatible: should be "mediatek,<name>-disp-pwm":
5 - "mediatek,mt2701-disp-pwm": found on mt2701 SoC.
6 - "mediatek,mt6595-disp-pwm": found on mt6595 SoC.
7 - "mediatek,mt8167-disp-pwm", "mediatek,mt8173-disp-pwm": found on mt8167 SoC.
8 - "mediatek,mt8173-disp-pwm": found on mt8173 SoC.
9 - "mediatek,mt8183-disp-pwm": found on mt8183 SoC.$
10 - reg: physical base address and length of the controller's registers.
11 - #pwm-cells: must be 2. See pwm.yaml in this directory for a description of
13 - clocks: phandle and clock specifier of the PWM reference clock.
14 - clock-names: must contain the following:
15 - "main": clock used to generate PWM signals.
16 - "mm": sync signals from the modules of mmsys.
17 - pinctrl-names: Must contain a "default" entry.
18 - pinctrl-0: One property must exist for each entry in pinctrl-names.
19 See pinctrl/pinctrl-bindings.txt for details of the property values.
22 pwm0: pwm@1401e000 {
23 compatible = "mediatek,mt8173-disp-pwm",
24 "mediatek,mt6595-disp-pwm";
26 #pwm-cells = <2>;
29 clock-names = "main", "mm";
30 pinctrl-names = "default";
31 pinctrl-0 = <&disp_pwm0_pins>;
35 compatible = "pwm-backlight";
37 brightness-levels = <
42 default-brightness-level = <9>;
43 power-supply = <&mt6397_vio18_reg>;
44 enable-gpios = <&pio 95 GPIO_ACTIVE_HIGH>;