Lines Matching +full:mt6795 +full:- +full:topckgen

4  - compatible: should be "mediatek,<name>-pwm":
5    - "mediatek,mt2712-pwm": found on mt2712 SoC.
6    - "mediatek,mt6795-pwm": found on mt6795 SoC.
7    - "mediatek,mt7622-pwm": found on mt7622 SoC.
8    - "mediatek,mt7623-pwm": found on mt7623 SoC.
9    - "mediatek,mt7628-pwm": found on mt7628 SoC.
10    - "mediatek,mt7629-pwm": found on mt7629 SoC.
11    - "mediatek,mt8183-pwm": found on mt8183 SoC.
12    - "mediatek,mt8195-pwm", "mediatek,mt8183-pwm": found on mt8195 SoC.
13    - "mediatek,mt8365-pwm": found on mt8365 SoC.
14    - "mediatek,mt8516-pwm": found on mt8516 SoC.
15  - reg: physical base address and length of the controller's registers.
16  - #pwm-cells: must be 2. See pwm.yaml in this directory for a description of
18  - clocks: phandle and clock specifier of the PWM reference clock.
19  - clock-names: must contain the following, except for MT7628 which
21    - "top": the top clock generator
22    - "main": clock used by the PWM core
23    - "pwm1-3": the three per PWM clocks for mt8365
24    - "pwm1-8": the eight per PWM clocks for mt2712
25    - "pwm1-6": the six per PWM clocks for mt7622
26    - "pwm1-5": the five per PWM clocks for mt7623
27    - "pwm1"  : the PWM1 clock for mt7629
28  - pinctrl-names: Must contain a "default" entry.
29  - pinctrl-0: One property must exist for each entry in pinctrl-names.
30    See pinctrl/pinctrl-bindings.txt for details of the property values.
33 - assigned-clocks: Reference to the PWM clock entries.
34 - assigned-clock-parents: The phandle of the parent clock of PWM clock.
38 		compatible = "mediatek,mt7623-pwm";
40 		#pwm-cells = <2>;
41 		clocks = <&topckgen CLK_TOP_PWM_SEL>,
48 		clock-names = "top", "main", "pwm1", "pwm2",
50 		pinctrl-names = "default";
51 		pinctrl-0 = <&pwm0_pins>;