Lines Matching +full:1 +full:- +full:cell

14   - compatible
22   - reg
24       Value type: <prop-encoded-array>
29   - interrupt-controller
35   - #interrupt-cells
39           specifiers do not contain the interrupt-type or type-specific
42   - #address-cells
47   - pic-no-reset
53           configuration registers to a sane state-- masked or
60   - big-endian
63           If present the MPIC will be assumed to be big-endian.  Some
64           device-trees omit this property on MPIC nodes even when the MPIC is
65           in fact big-endian, so certain boards override this property.
67   - single-cpu-affinity
71           non-IPI interrupts to a single CPU at a time (EG: Freescale MPIC).
73   - last-interrupt-source
85    <1st-cell>   interrupt-number
90                 Note: If the interrupt-type cell is undefined
91                 (i.e. #interrupt-cells = 2), this cell
93                 interrupt-type 0-- i.e. an external or
96    <2nd-cell>   level-sense information, encoded as follows:
97                     0 = low-to-high edge triggered
98                     1 = active low level-sensitive
99                     2 = active high level-sensitive
100                     3 = high-to-low edge triggered
102    <3rd-cell>   interrupt-type
108                       The interrupt-number cell contains
110                       type-specific cell is undefined.  The
111                       interrupt-number is derived from the
114                       Each source has 32-bytes of registers
117                       interrupt 1 is at offset 0x20, and so on.
119                   1 = error interrupt
121                       The interrupt-number cell contains
123                       the error interrupt.  The type-specific
124                       cell identifies the specific error
127                   2 = MPIC inter-processor interrupt (IPI)
129                       The interrupt-number cell identifies
130                       the MPIC IPI number.  The type-specific
131                       cell is undefined.
135                       The interrupt-number cell identifies
136                       the MPIC timer number.  The type-specific
137                       cell is undefined.
139    <4th-cell>   type-specific information
141                 The type-specific cell is encoded as follows:
143                  - For interrupt-type 1 (error interrupt),
144                    the type-specific cell contains the
148 EXAMPLE 1
154 		interrupt-controller;
155 		#interrupt-cells = <4>;
156 		#address-cells = <0>;
179 		#address-cells = <1>;
180 		#size-cells = <0>;
181 		cell-index = <0>;
182 		compatible = "fsl-i2c";
185 		interrupt-parent = <&mpic>;
197 		compatible = "fsl,mpic-ipi";
200 		              1 0 2 0
212 		compatible = "fsl,mpic-global-timer";
215 		              1 0 3 0
222 	 * Definition of an error interrupt (interrupt type 1).
227 	memory-controller@8000 {
228 		compatible = "fsl,p4080-memory-controller";
230 		interrupts = <16 2 1 23>;