Lines Matching +full:1 +full:- +full:cell
4 This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx
9 - compatible : must include "fsl,elo-dma"
10 - reg : DMA General Status Register, i.e. DGSR which contains
12 - ranges : describes the mapping between the address space of the
14 - cell-index : controller index. 0 for controller @ 0x8100
15 - interrupts : interrupt specifier for DMA IRQ
17 - DMA channel nodes:
18 - compatible : must include "fsl,elo-dma-channel"
20 - reg : DMA channel specific registers
21 - cell-index : DMA channel index starts at 0.
24 - interrupts : interrupt specifier for DMA channel IRQ
30 #address-cells = <1>;
31 #size-cells = <1>;
32 compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
35 interrupt-parent = <&ipic>;
37 cell-index = <0>;
38 dma-channel@0 {
39 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
40 cell-index = <0>;
42 interrupt-parent = <&ipic>;
45 dma-channel@80 {
46 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
47 cell-index = <1>;
49 interrupt-parent = <&ipic>;
52 dma-channel@100 {
53 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
54 cell-index = <2>;
56 interrupt-parent = <&ipic>;
59 dma-channel@180 {
60 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
61 cell-index = <3>;
63 interrupt-parent = <&ipic>;
69 This is a 4-channel DMA controller with extended addresses and chaining,
75 - compatible : must include "fsl,eloplus-dma"
76 - reg : DMA General Status Register, i.e. DGSR which contains
78 - cell-index : controller index. 0 for controller @ 0x21000,
79 1 for controller @ 0xc000
80 - ranges : describes the mapping between the address space of the
83 - DMA channel nodes:
84 - compatible : must include "fsl,eloplus-dma-channel"
86 - cell-index : DMA channel index starts at 0.
87 - reg : DMA channel specific registers
88 - interrupts : interrupt specifier for DMA channel IRQ
92 #address-cells = <1>;
93 #size-cells = <1>;
94 compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma";
97 cell-index = <0>;
98 dma-channel@0 {
99 compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
101 cell-index = <0>;
102 interrupt-parent = <&mpic>;
105 dma-channel@80 {
106 compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
108 cell-index = <1>;
109 interrupt-parent = <&mpic>;
112 dma-channel@100 {
113 compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
115 cell-index = <2>;
116 interrupt-parent = <&mpic>;
119 dma-channel@180 {
120 compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
122 cell-index = <3>;
123 interrupt-parent = <&mpic>;
135 - compatible : must include "fsl,elo3-dma"
136 - reg : contains two entries for DMA General Status Registers,
137 i.e. DGSR0 which includes status for channel 1~4, and
139 - ranges : describes the mapping between the address space of the
142 - DMA channel nodes:
143 - compatible : must include "fsl,eloplus-dma-channel"
144 - reg : DMA channel specific registers
145 - interrupts : interrupt specifier for DMA channel IRQ
149 #address-cells = <1>;
150 #size-cells = <1>;
151 compatible = "fsl,elo3-dma";
155 dma-channel@0 {
156 compatible = "fsl,eloplus-dma-channel";
160 dma-channel@80 {
161 compatible = "fsl,eloplus-dma-channel";
165 dma-channel@100 {
166 compatible = "fsl,eloplus-dma-channel";
170 dma-channel@180 {
171 compatible = "fsl,eloplus-dma-channel";
175 dma-channel@300 {
176 compatible = "fsl,eloplus-dma-channel";
180 dma-channel@380 {
181 compatible = "fsl,eloplus-dma-channel";
185 dma-channel@400 {
186 compatible = "fsl,eloplus-dma-channel";
190 dma-channel@480 {
191 compatible = "fsl,eloplus-dma-channel";
198 "fsl,elo-dma-channel" or "fsl,eloplus-dma-channel" to be used by the Elo DMA
202 "fsl,elo-dma-channel" or "fsl,eloplus-dma-channel". For the SSI drivers, for
203 example, the compatible property should be "fsl,ssi-dma-channel". See ssi.txt