Lines Matching +full:mt6795 +full:- +full:topckgen
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/mediatek,power-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - MandyJH Liu <mandyjh.liu@mediatek.com>
11 - Matthias Brugger <mbrugger@suse.com>
17 IP cores belonging to a power domain should contain a 'power-domains'
22 pattern: '^power-controller(@[0-9a-f]+)?$'
26 - mediatek,mt6795-power-controller
27 - mediatek,mt8167-power-controller
28 - mediatek,mt8173-power-controller
29 - mediatek,mt8183-power-controller
30 - mediatek,mt8186-power-controller
31 - mediatek,mt8188-power-controller
32 - mediatek,mt8192-power-controller
33 - mediatek,mt8195-power-controller
34 - mediatek,mt8365-power-controller
36 '#power-domain-cells':
39 '#address-cells':
42 '#size-cells':
46 "^power-domain@[0-9a-f]+$":
47 $ref: "#/$defs/power-domain-node"
49 "^power-domain@[0-9a-f]+$":
50 $ref: "#/$defs/power-domain-node"
52 "^power-domain@[0-9a-f]+$":
53 $ref: "#/$defs/power-domain-node"
55 "^power-domain@[0-9a-f]+$":
56 $ref: "#/$defs/power-domain-node"
63 power-domain-node:
67 in Documentation/devicetree/bindings/power/power-domain.yaml.
71 '#power-domain-cells':
76 '#address-cells':
79 '#size-cells':
85 "include/dt-bindings/power/mt6795-power.h" - for MT8167 type power domain.
86 "include/dt-bindings/power/mt8167-power.h" - for MT8167 type power domain.
87 "include/dt-bindings/power/mt8173-power.h" - for MT8173 type power domain.
88 "include/dt-bindings/power/mt8183-power.h" - for MT8183 type power domain.
89 "include/dt-bindings/power/mediatek,mt8188-power.h" - for MT8188 type power domain.
90 "include/dt-bindings/power/mt8192-power.h" - for MT8192 type power domain.
91 "include/dt-bindings/power/mt8195-power.h" - for MT8195 type power domain.
92 "include/dt-bindings/power/mediatek,mt8365-power.h" - for MT8365 type power domain.
98 power-up sequencing.
100 clock-names:
102 List of names of clocks, in order to match the power-up sequencing
105 domain, and should not have a '-' in their name (i.e mm, mfg, venc).
107 and should contain a '-' in their name (i.e mm-0, isp-0, cam-0).
109 In order to follow properly the power-up sequencing, the clocks must
113 domain-supply:
120 mediatek,infracfg-nao:
122 description: phandle to the device containing the INFRACFG-NAO register range.
129 - reg
132 - compatible
137 - |
138 #include <dt-bindings/clock/mt8173-clk.h>
139 #include <dt-bindings/power/mt8173-power.h>
142 #address-cells = <2>;
143 #size-cells = <2>;
146 compatible = "mediatek,mt8173-scpsys", "syscon", "simple-mfd";
149 spm: power-controller {
150 compatible = "mediatek,mt8173-power-controller";
151 #address-cells = <1>;
152 #size-cells = <0>;
153 #power-domain-cells = <1>;
156 power-domain@MT8173_POWER_DOMAIN_VDEC {
158 clocks = <&topckgen CLK_TOP_MM_SEL>;
159 clock-names = "mm";
160 #power-domain-cells = <0>;
162 power-domain@MT8173_POWER_DOMAIN_VENC {
164 clocks = <&topckgen CLK_TOP_MM_SEL>,
165 <&topckgen CLK_TOP_VENC_SEL>;
166 clock-names = "mm", "venc";
167 #power-domain-cells = <0>;
169 power-domain@MT8173_POWER_DOMAIN_ISP {
171 clocks = <&topckgen CLK_TOP_MM_SEL>;
172 clock-names = "mm";
173 #power-domain-cells = <0>;
175 power-domain@MT8173_POWER_DOMAIN_MM {
177 clocks = <&topckgen CLK_TOP_MM_SEL>;
178 clock-names = "mm";
179 #power-domain-cells = <0>;
182 power-domain@MT8173_POWER_DOMAIN_VENC_LT {
184 clocks = <&topckgen CLK_TOP_MM_SEL>,
185 <&topckgen CLK_TOP_VENC_LT_SEL>;
186 clock-names = "mm", "venclt";
187 #power-domain-cells = <0>;
189 power-domain@MT8173_POWER_DOMAIN_AUDIO {
191 #power-domain-cells = <0>;
193 power-domain@MT8173_POWER_DOMAIN_USB {
195 #power-domain-cells = <0>;
197 power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC {
200 clock-names = "mfg";
201 #address-cells = <1>;
202 #size-cells = <0>;
203 #power-domain-cells = <1>;
205 power-domain@MT8173_POWER_DOMAIN_MFG_2D {
207 #address-cells = <1>;
208 #size-cells = <0>;
209 #power-domain-cells = <1>;
211 power-domain@MT8173_POWER_DOMAIN_MFG {
213 #power-domain-cells = <0>;