Lines Matching +full:zynqmp +full:- +full:power

1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/xlnx,zynqmp-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx ZynqMP Pinctrl
10   - Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
13   Please refer to pinctrl-bindings.txt in this directory for details of the
17   ZynqMP's pin configuration nodes act as a container for an arbitrary number of
21   parameters, such as pull-up, slew rate, etc.
31     const: xlnx,zynqmp-pinctrl
34   '^(.*-)?(default|gpio-grp)$':
42         $ref: pinmux-node.yaml#
233           - groups
234           - function
243         $ref: pincfg-node.yaml#
254               pattern: '^MIO([0-9]|[1-6][0-9]|7[0-7])$'
257           bias-pull-up: true
259           bias-pull-down: true
261           bias-disable: true
263           input-schmitt-enable: true
265           input-schmitt-disable: true
267           bias-high-impedance: true
269           low-power-enable: true
271           low-power-disable: true
273           slew-rate:
276           output-enable:
278               This will internally disable the tri-state for MIO pins.
280           drive-strength:
285           power-source:
289           - required: [ groups ]
290           - required: [ pins ]
297   - $ref: pinctrl.yaml#
300   - compatible
305   - |
306     #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
307     zynqmp_firmware: zynqmp-firmware {
309           compatible = "xlnx,zynqmp-pinctrl";
311           pinctrl_uart1_default: uart1-default {
319                 slew-rate = <SLEW_RATE_SLOW>;
320                 power-source = <IO_STANDARD_LVCMOS18>;
323              conf-rx {
325                 bias-pull-up;
328              conf-tx {
330                 bias-disable;
331                 input-schmitt-disable;
338          pinctrl-names = "default";
339          pinctrl-0 = <&pinctrl_uart1_default>;