Lines Matching +full:- +full:gpio +full:- +full:bank
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/st,stm32-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: STM32 GPIO and Pin Mux/Config controller
11 - Alexandre TORGUE <alexandre.torgue@foss.st.com>
14 STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config hardware
17 on-chip controllers onto these pads.
22 - st,stm32f429-pinctrl
23 - st,stm32f469-pinctrl
24 - st,stm32f746-pinctrl
25 - st,stm32f769-pinctrl
26 - st,stm32h743-pinctrl
27 - st,stm32mp135-pinctrl
28 - st,stm32mp157-pinctrl
29 - st,stm32mp157-z-pinctrl
30 - st,stm32mp257-pinctrl
31 - st,stm32mp257-z-pinctrl
33 '#address-cells':
35 '#size-cells':
39 pins-are-numbered:
49 $ref: /schemas/types.yaml#/definitions/phandle-array
51 - minItems: 2
53 - description: syscon node which includes IRQ mux selection
54 - description: The offset of the IRQ mux selection register
55 - description: The field mask of IRQ mux, needed if different of 0xf
60 More details in include/dt-bindings/pinctrl/stm32-pinfunc.h
65 '^gpio@[0-9a-f]*$':
69 gpio-controller: true
70 '#gpio-cells':
72 interrupt-controller: true
73 '#interrupt-cells':
82 gpio-line-names: true
83 gpio-ranges:
88 Number of available gpios in a bank.
92 st,bank-name:
94 Should be a name string for this bank as specified in the datasheet.
97 - GPIOA
98 - GPIOB
99 - GPIOC
100 - GPIOD
101 - GPIOE
102 - GPIOF
103 - GPIOG
104 - GPIOH
105 - GPIOI
106 - GPIOJ
107 - GPIOK
108 - GPIOZ
110 st,bank-ioport:
119 "^(.+-hog(-[0-9]+)?)$":
122 - gpio-hog
125 - gpio-controller
126 - '#gpio-cells'
127 - reg
128 - clocks
129 - st,bank-name
131 '-[0-9]*$':
146 $ref: /schemas/types.yaml#/definitions/uint32-array
148 Integer array, represents gpio pin number and mux setting.
150 defined in dt-bindings/pinctrl/<soc>-pinfunc.h directly.
153 - port: The gpio port index (PA = 0, PB = 1, ..., PK = 11)
154 - line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15)
155 - function: The function number, can be:
156 * 0 : GPIO
165 - include/dt-bindings/pinctrl/stm32-pinfunc.h
167 /* GPIO A9 set as alernate function 2 */
171 /* GPIO A9 set as GPIO */
173 pinmux = <STM32_PINMUX('A', 9, GPIO)>;
175 /* GPIO A9 set as analog */
180 bias-disable:
182 bias-pull-down:
184 bias-pull-up:
186 drive-push-pull:
188 drive-open-drain:
190 output-low:
192 output-high:
194 slew-rate:
204 - pinmux
207 - $ref: pinctrl.yaml#
210 - compatible
211 - '#address-cells'
212 - '#size-cells'
213 - ranges
218 - |
219 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
220 #include <dt-bindings/mfd/stm32f4-rcc.h>
223 #address-cells = <1>;
224 #size-cells = <1>;
225 compatible = "st,stm32f429-pinctrl";
228 gpioa: gpio@0 {
229 gpio-controller;
230 #gpio-cells = <2>;
234 st,bank-name = "GPIOA";
238 //Example 2 (using gpio-ranges)
240 #address-cells = <1>;
241 #size-cells = <1>;
242 compatible = "st,stm32f429-pinctrl";
245 gpiob: gpio@1000 {
246 gpio-controller;
247 #gpio-cells = <2>;
251 st,bank-name = "GPIOB";
252 gpio-ranges = <&pinctrl 0 0 16>;
255 gpioc: gpio@2000 {
256 gpio-controller;
257 #gpio-cells = <2>;
261 st,bank-name = "GPIOC";
263 gpio-ranges = <&pinctrl 0 16 3>,
270 usart1_pins_a: usart1-0 {
273 bias-disable;
274 drive-push-pull;
275 slew-rate = <0>;
279 bias-disable;
285 pinctrl-0 = <&usart1_pins_a>;
286 pinctrl-names = "default";