Lines Matching +full:soc +full:- +full:gpio10
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,mdm9615-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
12 description: Top Level Mode Multiplexer pin controller in Qualcomm MDM9615 SoC.
14 $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
18 const: qcom,mdm9615-pinctrl
27 "-state$":
29 - $ref: "#/$defs/qcom-mdm9615-pinctrl-state"
30 - patternProperties:
31 "-pins$":
32 $ref: "#/$defs/qcom-mdm9615-pinctrl-state"
36 qcom-mdm9615-pinctrl-state:
41 $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
50 pattern: "^gpio([0-9]|[1-7][0-9]|8[0-7])$"
63 - pins
66 - compatible
67 - reg
72 - |
73 #include <dt-bindings/interrupt-controller/arm-gic.h>
75 compatible = "qcom,mdm9615-pinctrl";
78 gpio-controller;
79 gpio-ranges = <&msmgpio 0 0 88>;
80 #gpio-cells = <2>;
81 interrupt-controller;
82 #interrupt-cells = <2>;
84 gsbi3-state {
85 pins = "gpio8", "gpio9", "gpio10", "gpio11";
87 drive-strength = <8>;
88 bias-disable;
91 gsbi5-i2c-state {
92 sda-pins {
95 drive-strength = <8>;
96 bias-disable;
99 scl-pins {
102 drive-strength = <2>;
103 bias-disable;