Lines Matching +full:non +full:- +full:inverted
3 Each multi-function pin is controlled, driven and routed through the
5 and multiple alternate functions(ALT1 - ALTx) that directly connect
14 GPIO bank can have one of the two possible types of interrupt-wirings.
20 | |----> [gpio-bank (n) ]
21 | |----> [gpio-bank (n + 1)]
22 [irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
23 | |----> [gpio-bank (... )]
24 |_________|----> [gpio-bank (n + 7)]
28 [irqN]----> [gpio-bank (n)]
33 - compatible : should be "st,stih407-<pio-block>-pinctrl"
34 - st,syscfg : Should be a phandle of the syscfg node.
35 - st,retime-pin-mask : Should be mask to specify which pins can be retimed.
39 - ranges : defines mapping between pin controller node (parent) to gpio-bank
43 - interrupts : Interrupt number of the irqmux. If the interrupt is shared
46 - reg : irqmux memory resource. If irqmux is present.
47 - reg-names : irqmux resource should be named as "irqmux".
51 - gpio-controller : Indicates this device is a GPIO controller
52 - #gpio-cells : Must be two.
53 - First cell: specifies the pin number inside the controller
54 - Second cell: specifies whether the pin is logically inverted.
55 - 0 = active high
56 - 1 = active low
57 - st,bank-name : Should be a name string for this bank as specified in
61 - interrupts : Interrupt number for this gpio bank. If there is a dedicated
64 - interrupt-controller : Indicates this device is a interrupt controller. GPIO
68 - #interrupt-cells: the value of this property should be 2.
69 - First Cell: represents the external gpio interrupt number local to the
71 - Second Cell: flags to identify the type of the interrupt
72 - 1 = rising edge triggered
73 - 2 = falling edge triggered
74 - 3 = rising and falling edge triggered
75 - 4 = high level triggered
76 - 8 = low level triggered
78 include/dt-bindings/interrupt-controller/irq.h
81 pin-controller-sbc {
82 #address-cells = <1>;
83 #size-cells = <1>;
84 compatible = "st,stih407-sbc-pinctrl";
87 reg-names = "irqmux";
89 interrupt-names = "irqmux";
93 gpio-controller;
94 #gpio-cells = <2>;
95 interrupt-controller;
96 #interrupt-cells = <2>;
98 st,bank-name = "PIO0";
101 pin-functions nodes follow...
106 ----------------------
108 - st,pins : Child node with list of pins with configuration.
114 Every PIO is represented with 4-7 parameters depending on retime configuration.
117 -bank : Should be bank phandle to which this PIO belongs.
118 -offset : Offset in the PIO bank.
119 -mux : Should be alternate function number associated this pin.
121 -mode :pin configuration is selected from one of the below values.
128 -rt_type Retiming Configuration for the pin.
131 ------- -------------
133 ------- -------------
141 - delay is retime delay in pico seconds as mentioned in data sheet.
143 - rt_clk :clk to be use for retime.
150 Example of mmcclk pin which is a bi-direction pull pu with retime config
151 as non inverted clock retimed with CLK_B and delay of 0 pico seconds:
153 pin-controller {
168 interrupt-parent = <&pio3>;
169 #interrupt-cells = <2>;
170 interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; /* Interrupt line via PIO3-3 */
171 interrupt-names = "card-detect";
172 pinctrl-names = "default";
173 pinctrl-0 = <&pinctrl_mmc>;