Lines Matching +full:grp0 +full:- +full:pinmux
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/nxp,s32g2-siul2-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Ghennadi Procopciuc <Ghennadi.Procopciuc@oss.nxp.com>
12 - Chester Lin <chester62515@gmail.com>
15 S32G2 pinmux is implemented in SIUL2 (System Integration Unit Lite2),
21 IMCR registers need to be revealed for kernel to configure pinmux.
24 MSCR102-MSCR111, MSCR123-MSCR143, IMCR84-IMCR118 and IMCR398-IMCR429.
29 - nxp,s32g2-siul2-pinctrl
34 - MSCR (Multiplexed Signal Configuration Register)
37 - IMCR (Input Multiplexed Signal Configuration Register)
41 - description: MSCR registers group 0 in SIUL2_0
42 - description: MSCR registers group 1 in SIUL2_1
43 - description: MSCR registers group 2 in SIUL2_1
44 - description: IMCR registers group 0 in SIUL2_0
45 - description: IMCR registers group 1 in SIUL2_1
46 - description: IMCR registers group 2 in SIUL2_1
49 '-pins$':
54 '-grp[0-9]$':
57 - $ref: pinmux-node.yaml#
58 - $ref: pincfg-node.yaml#
64 bias-disable: true
65 bias-high-impedance: true
66 bias-pull-up: true
67 bias-pull-down: true
68 drive-open-drain: true
69 input-enable: true
70 output-enable: true
72 pinmux:
74 An integer array for representing pinmux configurations of
75 a device. Each integer consists of a PIN_ID and a 4-bit
77 calculated as: pinmux = (PIN_ID << 4 | SSS)
79 slew-rate:
86 - compatible
87 - reg
92 - |
94 compatible = "nxp,s32g2-siul2-pinctrl";
96 /* MSCR0-MSCR101 registers on siul2_0 */
98 /* MSCR112-MSCR122 registers on siul2_1 */
100 /* MSCR144-MSCR190 registers on siul2_1 */
102 /* IMCR0-IMCR83 registers on siul2_0 */
104 /* IMCR119-IMCR397 registers on siul2_1 */
106 /* IMCR430-IMCR495 registers on siul2_1 */
109 llce-can0-pins {
110 llce-can0-grp0 {
111 pinmux = <0x2b0>;
112 input-enable;
113 slew-rate = <208>;
116 llce-can0-grp1 {
117 pinmux = <0x2c2>;
118 output-enable;
119 slew-rate = <208>;