Lines Matching +full:tegra210 +full:- +full:qspi

1 NVIDIA Tegra210 pinmux controller
4 - compatible: "nvidia,tegra210-pinmux"
5 - reg: Should contain a list of base address and size pairs for:
6   - first entry: The APB_MISC_GP_*_PADCTRL registers (pad control)
7   - second entry: The PINMUX_AUX_* registers (pinmux)
9 Please refer to pinctrl-bindings.txt in this directory for details of the
17 parameters, such as pull-up, tristate, drive strength, etc.
33 include/dt-binding/pinctrl/pinctrl-tegra.h.
35 Required subnode-properties:
36 - nvidia,pins : An array of strings. Each string contains the name of a pin or
39 Optional subnode-properties:
40 - nvidia,function: A string containing the name of the function to mux to the
42 - nvidia,pull: Integer, representing the pull-down/up to apply to the pin.
44 - nvidia,tristate: Integer.
46 - nvidia,enable-input: Integer. Enable the pin's input path.
49 - nvidia,open-drain: Integer.
52 - nvidia,lock: Integer. Lock the pin configuration against further changes
56 - nvidia,io-hv: Integer. Select high-voltage receivers.
59 - nvidia,high-speed-mode: Integer. Enable high speed mode the pins.
62 - nvidia,schmitt: Integer. Enables Schmitt Trigger on the input.
65 - nvidia,drive-type: Integer. Valid range 0...3.
66 - nvidia,pull-down-strength: Integer. Controls drive strength. 0 is weakest.
69 - nvidia,pull-up-strength: Integer. Controls drive strength. 0 is weakest.
72 - nvidia,slew-rate-rising: Integer. Controls rising signal slew rate. 0 is
75 - nvidia,slew-rate-falling: Integer. Controls falling signal slew rate. 0 is
86     In Tegra210, many pins also have a dedicated APB_MISC_GP_*_PADCTRL
139     pe1, pmi, pwm0, pwm1, pwm2, pwm3, qspi, rsvd0, rsvd1, rsvd2, rsvd3, sata,
147 		compatible = "nvidia,tegra210-pinmux";
151 		pinctrl-names = "boot";
152 		pinctrl-0 = <&state_boot>;
160 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
161 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
162 				nvidia,io-hv = <TEGRA_PIN_ENABLE>;