Lines Matching +full:tegra20 +full:- +full:hdmi

1 NVIDIA Tegra20 pinmux controller
4 - compatible: "nvidia,tegra20-pinmux"
5 - reg: Should contain the register physical address and length for each of
6   the tri-state, mux, pull-up/down, and pad control register sets.
8 Please refer to pinctrl-bindings.txt in this directory for details of the
16 parameters, such as pull-up, tristate, drive strength, etc.
30 Required subnode-properties:
31 - nvidia,pins : An array of strings. Each string contains the name of a pin or
34 Optional subnode-properties:
35 - nvidia,function: A string containing the name of the function to mux to the
38 - nvidia,pull: Integer, representing the pull-down/up to apply to the pin.
40 - nvidia,tristate: Integer.
42 - nvidia,high-speed-mode: Integer. Enable high speed mode the pins.
44 - nvidia,schmitt: Integer. Enables Schmitt Trigger on the input.
46 - nvidia,low-power-mode: Integer. Valid values 0-3. 0 is least power, 3 is
49 - nvidia,pull-down-strength: Integer. Controls drive strength. 0 is weakest.
52 - nvidia,pull-up-strength: Integer. Controls drive strength. 0 is weakest.
55 - nvidia,slew-rate-rising: Integer. Controls rising signal slew rate. 0 is
58 - nvidia,slew-rate-falling: Integer. Controls falling signal slew rate. 0 is
94     With some exceptions, these support nvidia,high-speed-mode,
95     nvidia,schmitt, nvidia,low-power-mode, nvidia,pull-down-strength,
96     nvidia,pull-up-strength, nvidia,slew-rate-rising, nvidia,slew-rate-falling.
110   hdmi, i2cp, i2c1, i2c2, i2c3, ide, irda, kbc, mio, mipi_hs, nand,
120 		compatible = "nvidia,tegra20-pinmux";
121 		reg = < 0x70000014 0x10    /* Tri-state registers */
123 			0x700000a0 0x14    /* Pull-up/down registers */
141 		pinctrl-names = "default";
142 		pinctrl-0 = <&sdio4_default>;