Lines Matching +full:sparx5 +full:- +full:switch +full:- +full:reset
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mscc,ocelot-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Belloni <alexandre.belloni@bootlin.com>
11 - Lars Povlsen <lars.povlsen@microchip.com>
16 - microchip,lan966x-pinctrl
17 - microchip,sparx5-pinctrl
18 - mscc,jaguar2-pinctrl
19 - mscc,luton-pinctrl
20 - mscc,ocelot-pinctrl
21 - mscc,serval-pinctrl
22 - mscc,servalt-pinctrl
26 - description: Base address
27 - description: Extended pin configuration registers
30 gpio-controller: true
32 '#gpio-cells':
35 gpio-ranges: true
40 interrupt-controller: true
42 "#interrupt-cells":
48 reset-names:
49 description: Optional shared switch reset.
51 - const: switch
54 '-pins$':
57 - $ref: pinmux-node.yaml
58 - $ref: pincfg-node.yaml
63 output-high: true
64 output-low: true
65 drive-strength: true
68 - function
69 - pins
74 - compatible
75 - reg
76 - gpio-controller
77 - '#gpio-cells'
78 - gpio-ranges
81 - $ref: pinctrl.yaml#
82 - if:
87 - microchip,lan966x-pinctrl
88 - microchip,sparx5-pinctrl
97 - |
99 compatible = "mscc,ocelot-pinctrl";
101 gpio-controller;
102 #gpio-cells = <2>;
103 gpio-ranges = <&gpio 0 0 22>;
105 uart_pins: uart-pins {
110 uart2_pins: uart2-pins {