Lines Matching +full:pwr +full:- +full:sel
5 - compatible:
6 "brcm,iproc-gpio" for the generic iProc based GPIO controller IP that
7 supports full-featured pinctrl and GPIO functions used in various iProc
10 May contain an SoC-specific compatibility string to accommodate any
11 SoC-specific features
13 "brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio", or
14 "brcm,cygnus-crmu-gpio" for Cygnus SoCs
16 "brcm,iproc-nsp-gpio" for the iProc NSP SoC that has drive strength support
19 "brcm,iproc-stingray-gpio" for the iProc Stingray SoC that has the general
23 - reg:
27 - ngpios:
28 Total number of in-use slots in GPIO controller
30 - #gpio-cells:
35 - gpio-controller:
40 - interrupts:
43 - interrupt-controller:
46 - gpio-ranges:
47 Specifies the mapping between gpio controller and pin-controllers pins.
48 This requires 4 fields in cells defined as -
49 1. Phandle of pin-controller.
51 3 Pin-control base pin offset.
56 - pins:
58 in the node apply to. Pin names are "gpio-<pin>"
60 - bias-disable:
63 - bias-pull-up:
66 - bias-pull-down:
69 - drive-strength:
74 compatible = "brcm,cygnus-ccm-gpio";
78 #gpio-cells = <2>;
79 gpio-controller;
81 interrupt-controller;
84 pwr: pwr {
85 pins = "gpio-0";
86 drive-strength = <16>;
90 pins = "gpio-1";
91 bias-pull-up;
97 compatible = "brcm,cygnus-asiu-gpio";
100 #gpio-cells = <2>;
101 gpio-controller;
103 interrupt-controller;
104 gpio-ranges = <&pinctrl 0 42 1>,
114 gpio-pwr = <&gpio_ccm 0 0>;
115 gpio-event = <&gpio_ccm 1 0>;
122 bcm,rfkill-bank-sel = <&gpio_asiu 5 1>