Lines Matching full:phy
4 $id: http://devicetree.org/schemas/phy/samsung,usb3-drd-phy.yaml#
7 title: Samsung Exynos SoC USB 3.0 DRD PHY USB 2.0 PHY
15 For samsung,exynos5250-usbdrd-phy and samsung,exynos5420-usbdrd-phy
16 compatible PHYs, the second cell in the PHY specifier identifies the
17 PHY id, which is interpreted as follows::
18 0 - UTMI+ type phy,
19 1 - PIPE3 type phy.
21 For SoCs like Exynos5420 having multiple USB 3.0 DRD PHY controllers,
28 - google,gs101-usb31drd-phy
29 - samsung,exynos5250-usbdrd-phy
30 - samsung,exynos5420-usbdrd-phy
31 - samsung,exynos5433-usbdrd-phy
32 - samsung,exynos7-usbdrd-phy
33 - samsung,exynos850-usbdrd-phy
44 - Main PHY clock (same as USB DRD controller i.e. DWC3 IP clock), used
46 - PHY reference clock (usually crystal clock), used for PHY operations,
47 associated by phy name. It is used to determine bit values for clock
51 "#phy-cells":
67 - const: phy
87 description: DVDD power supply for the USB 2.0 phy.
89 description: VDDh power supply for the USB 2.0 phy.
91 description: 3.3V power supply for the USB 2.0 phy.
93 description: VDDa power supply for the USB DP phy.
95 description: VDDh power supply for the USB DP phy.
101 - "#phy-cells"
110 const: google,gs101-usb31drd-phy
115 - description: Gate of main PHY clock
116 - description: Gate of PHY reference clock
122 - const: phy
145 - samsung,exynos5433-usbdrd-phy
146 - samsung,exynos7-usbdrd-phy
154 - const: phy
169 - samsung,exynos5250-usbdrd-phy
170 - samsung,exynos5420-usbdrd-phy
171 - samsung,exynos850-usbdrd-phy
179 - const: phy
192 phy@12100000 {
193 compatible = "samsung,exynos5420-usbdrd-phy";
195 #phy-cells = <1>;
197 clock-names = "phy", "ref";