Lines Matching +full:phy +full:- +full:grf

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip-inno-csi-dphy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SoC MIPI RX0 D-PHY
10   - Heiko Stuebner <heiko@sntech.de>
13   The Rockchip SoC has a MIPI CSI D-PHY based on an Innosilicon IP which
19       - rockchip,px30-csi-dphy
20       - rockchip,rk1808-csi-dphy
21       - rockchip,rk3326-csi-dphy
22       - rockchip,rk3368-csi-dphy
23       - rockchip,rk3568-csi-dphy
31   clock-names:
34   '#phy-cells':
37   power-domains:
43       - description: exclusive PHY reset line
45   reset-names:
47       - const: apb
49   rockchip,grf:
52       Some additional phy settings are access through GRF regs.
55   - compatible
56   - reg
57   - clocks
58   - clock-names
59   - '#phy-cells'
60   - power-domains
61   - resets
62   - reset-names
63   - rockchip,grf
68   - |
70     csi_dphy: phy@ff2f0000 {
71         compatible = "rockchip,px30-csi-dphy";
74         clock-names = "pclk";
75         #phy-cells = <0>;
76         power-domains = <&power 1>;
78         reset-names = "apb";
79         rockchip,grf = <&grf>;