Lines Matching +full:phy +full:- +full:grf
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip PCIe v3 phy
10 - Heiko Stuebner <heiko@sntech.de>
15 - rockchip,rk3568-pcie3-phy
16 - rockchip,rk3588-pcie3-phy
25 clock-names:
29 data-lanes:
32 (controller-number +1 )
33 $ref: /schemas/types.yaml#/definitions/uint32-array
40 "#phy-cells":
46 reset-names:
47 const: phy
49 rockchip,phy-grf:
51 description: phandle to the syscon managing the phy "general register files"
53 rockchip,pipe-grf:
58 - compatible
59 - reg
60 - rockchip,phy-grf
61 - "#phy-cells"
64 - if:
68 - rockchip,rk3588-pcie3-phy
73 clock-names:
75 - const: pclk
81 clock-names:
83 - const: refclk_m
84 - const: refclk_n
85 - const: pclk
90 - |
91 #include <dt-bindings/clock/rk3568-cru.h>
92 pcie30phy: phy@fe8c0000 {
93 compatible = "rockchip,rk3568-pcie3-phy";
95 #phy-cells = <0>;
99 clock-names = "refclk_m", "refclk_n", "pclk";
101 reset-names = "phy";
102 rockchip,phy-grf = <&pcie30_phy_grf>;