Lines Matching +full:otg +full:- +full:vbus
1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip,inno-usb2phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
15 - rockchip,px30-usb2phy
16 - rockchip,rk3128-usb2phy
17 - rockchip,rk3228-usb2phy
18 - rockchip,rk3308-usb2phy
19 - rockchip,rk3328-usb2phy
20 - rockchip,rk3366-usb2phy
21 - rockchip,rk3399-usb2phy
22 - rockchip,rk3568-usb2phy
23 - rockchip,rk3588-usb2phy
24 - rockchip,rv1108-usb2phy
29 clock-output-names:
33 "#clock-cells":
39 clock-names:
42 assigned-clocks:
46 assigned-clock-parents:
49 Select between usb-phy output 480m and xin24m.
50 Refer to clk/clock-bindings.txt for generic clock consumer properties.
54 Phandle to the extcon device providing the cable state for the otg phy.
63 reset-names:
65 - const: phy
66 - const: apb
72 When set the driver will request its phandle as one companion-grf
75 host-port:
80 "#phy-cells":
87 interrupt-names:
90 phy-supply:
92 Phandle to a regulator that provides power to VBUS.
93 See ./phy-bindings.txt for details.
96 - "#phy-cells"
98 otg-port:
103 "#phy-cells":
110 interrupt-names:
112 - const: linestate
113 - const: otg-mux
114 - items:
115 - const: otg-bvalid
116 - const: otg-id
117 - const: linestate
119 phy-supply:
121 Phandle to a regulator that provides power to VBUS.
122 See ./phy-bindings.txt for details.
125 - "#phy-cells"
128 - compatible
129 - reg
130 - clock-output-names
131 - "#clock-cells"
134 - required:
135 - otg-port
136 - required:
137 - host-port
140 - if:
145 - rockchip,rk3568-usb2phy
146 - rockchip,rk3588-usb2phy
150 host-port:
154 otg-port:
159 - interrupts
165 host-port:
167 - interrupts
168 - interrupt-names
170 otg-port:
172 - interrupts
173 - interrupt-names
178 - |
179 #include <dt-bindings/clock/rk3399-cru.h>
180 #include <dt-bindings/interrupt-controller/arm-gic.h>
181 #include <dt-bindings/interrupt-controller/irq.h>
183 compatible = "rockchip,rk3399-usb2phy";
186 clock-names = "phyclk";
187 clock-output-names = "clk_usbphy0_480m";
188 #clock-cells = <0>;
190 u2phy0_host: host-port {
192 interrupt-names = "linestate";
193 #phy-cells = <0>;
196 u2phy0_otg: otg-port {
200 interrupt-names = "otg-bvalid", "otg-id", "linestate";
201 #phy-cells = <0>;