Lines Matching +full:aux +full:- +full:output +full:- +full:power
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/qcom,sc7180-qmp-usb3-dp-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 qcom,sc8280xp-qmp-usb43dp-phy.yaml.
18 - Wesley Cheng <quic_wcheng@quicinc.com>
23 - enum:
24 - qcom,sc7180-qmp-usb3-dp-phy
25 - qcom,sc8180x-qmp-usb3-dp-phy
26 - qcom,sdm845-qmp-usb3-dp-phy
27 - qcom,sm8250-qmp-usb3-dp-phy
28 - items:
29 - enum:
30 - qcom,sc7280-qmp-usb3-dp-phy
31 - const: qcom,sm8250-qmp-usb3-dp-phy
35 - description: Address and length of PHY's USB serdes block.
36 - description: Address and length of the DP_COM control block.
37 - description: Address and length of PHY's DP serdes block.
39 reg-names:
41 - const: usb
42 - const: dp_com
43 - const: dp
45 "#address-cells":
48 "#size-cells":
57 clock-names:
61 power-domains:
64 orientation-switch:
70 - description: reset of phy block.
71 - description: phy common block reset.
73 reset-names:
75 - const: phy
76 - const: common
78 vdda-phy-supply:
82 vdda-pll-supply:
86 vddp-ref-clk-supply:
92 "^usb3-phy@[0-9a-f]+$":
101 - description: Address and length of TX.
102 - description: Address and length of RX.
103 - description: Address and length of PCS.
104 - description: Address and length of TX2.
105 - description: Address and length of RX2.
106 - description: Address and length of pcs_misc.
110 - description: pipe clock
112 clock-names:
115 - const: pipe0
117 clock-output-names:
119 - const: usb3_phy_pipe_clk_src
121 '#clock-cells':
124 '#phy-cells':
128 - reg
129 - clocks
130 - '#clock-cells'
131 - '#phy-cells'
133 "^dp-phy@[0-9a-f]+$":
142 - description: Address and length of TX.
143 - description: Address and length of RX.
144 - description: Address and length of PCS.
145 - description: Address and length of TX2.
146 - description: Address and length of RX2.
148 '#clock-cells':
151 '#phy-cells':
155 - reg
156 - '#clock-cells'
157 - '#phy-cells'
160 - compatible
161 - reg
162 - "#address-cells"
163 - "#size-cells"
164 - ranges
165 - clocks
166 - clock-names
167 - resets
168 - reset-names
169 - vdda-phy-supply
170 - vdda-pll-supply
173 - if:
177 - qcom,sc7180-qmp-usb3-dp-phy
178 - qcom,sdm845-qmp-usb3-dp-phy
183 - description: Phy aux clock
184 - description: Phy config clock
185 - description: 19.2 MHz ref clk
186 - description: Phy common block aux clock
187 clock-names:
189 - const: aux
190 - const: cfg_ahb
191 - const: ref
192 - const: com_aux
194 - if:
198 - qcom,sc8180x-qmp-usb3-dp-phy
203 - description: Phy aux clock
204 - description: 19.2 MHz ref clk
205 - description: Phy common block aux clock
206 clock-names:
208 - const: aux
209 - const: ref
210 - const: com_aux
212 - if:
216 - qcom,sm8250-qmp-usb3-dp-phy
221 - description: Phy aux clock
222 - description: Board XO source
223 - description: Phy common block aux clock
224 clock-names:
226 - const: aux
227 - const: ref_clk_src
228 - const: com_aux
233 - |
234 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
235 usb_1_qmpphy: phy-wrapper@88e9000 {
236 compatible = "qcom,sdm845-qmp-usb3-dp-phy";
240 reg-names = "usb", "dp_com", "dp";
241 #address-cells = <1>;
242 #size-cells = <1>;
249 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
253 reset-names = "phy", "common";
255 vdda-phy-supply = <&vdda_usb2_ss_1p2>;
256 vdda-pll-supply = <&vdda_usb2_ss_core>;
258 orientation-switch;
260 usb3-phy@200 {
267 #clock-cells = <0>;
268 #phy-cells = <0>;
270 clock-output-names = "usb3_phy_pipe_clk_src";
273 dp-phy@88ea200 {
279 #clock-cells = <1>;
280 #phy-cells = <0>;