Lines Matching full:phy
5 $id: http://devicetree.org/schemas/phy/qcom,sc7180-qmp-usb3-dp-phy.yaml#
8 title: Qualcomm QMP USB3 DP PHY controller (SC7180)
11 The QMP PHY controller supports physical layer functionality for a number of
15 qcom,sc8280xp-qmp-usb43dp-phy.yaml.
24 - qcom,sc7180-qmp-usb3-dp-phy
25 - qcom,sc8180x-qmp-usb3-dp-phy
26 - qcom,sdm845-qmp-usb3-dp-phy
27 - qcom,sm8250-qmp-usb3-dp-phy
30 - qcom,sc7280-qmp-usb3-dp-phy
31 - const: qcom,sm8250-qmp-usb3-dp-phy
35 - description: Address and length of PHY's USB serdes block.
37 - description: Address and length of PHY's DP serdes block.
70 - description: reset of phy block.
71 - description: phy common block reset.
75 - const: phy
78 vdda-phy-supply:
80 Phandle to a regulator supply to PHY core block.
84 Phandle to 1.8V regulator supply to PHY refclk pll block.
92 "^usb3-phy@[0-9a-f]+$":
96 The USB3 PHY.
124 '#phy-cells':
131 - '#phy-cells'
133 "^dp-phy@[0-9a-f]+$":
137 The DP PHY.
151 '#phy-cells':
157 - '#phy-cells'
169 - vdda-phy-supply
177 - qcom,sc7180-qmp-usb3-dp-phy
178 - qcom,sdm845-qmp-usb3-dp-phy
183 - description: Phy aux clock
184 - description: Phy config clock
186 - description: Phy common block aux clock
198 - qcom,sc8180x-qmp-usb3-dp-phy
203 - description: Phy aux clock
205 - description: Phy common block aux clock
216 - qcom,sm8250-qmp-usb3-dp-phy
221 - description: Phy aux clock
223 - description: Phy common block aux clock
235 usb_1_qmpphy: phy-wrapper@88e9000 {
236 compatible = "qcom,sdm845-qmp-usb3-dp-phy";
253 reset-names = "phy", "common";
255 vdda-phy-supply = <&vdda_usb2_ss_1p2>;
260 usb3-phy@200 {
268 #phy-cells = <0>;
273 dp-phy@88ea200 {
280 #phy-cells = <0>;