Lines Matching +full:serdes +full:- +full:clk
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,qmp-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vinod Koul <vkoul@kernel.org>
19 - qcom,ipq6018-qmp-pcie-phy
20 - qcom,ipq8074-qmp-gen3-pcie-phy
21 - qcom,ipq8074-qmp-pcie-phy
22 - qcom,msm8998-qmp-pcie-phy
23 - qcom,sc8180x-qmp-pcie-phy
24 - qcom,sdm845-qhp-pcie-phy
25 - qcom,sdm845-qmp-pcie-phy
26 - qcom,sdx55-qmp-pcie-phy
27 - qcom,sm8250-qmp-gen3x1-pcie-phy
28 - qcom,sm8250-qmp-gen3x2-pcie-phy
29 - qcom,sm8250-qmp-modem-pcie-phy
30 - qcom,sm8450-qmp-gen3x1-pcie-phy
31 - qcom,sm8450-qmp-gen4x2-pcie-phy
35 - description: serdes
37 "#address-cells":
40 "#size-cells":
49 clock-names:
57 reset-names:
61 vdda-phy-supply: true
63 vdda-pll-supply: true
65 vddp-ref-clk-supply: true
68 "^phy@[0-9a-f]+$":
70 description: single PHY-provider child node
78 - description: PIPE clock
80 clock-names:
83 - const: pipe0
85 "#clock-cells":
88 clock-output-names:
91 "#phy-cells":
95 - reg
96 - clocks
97 - "#clock-cells"
98 - clock-output-names
99 - "#phy-cells"
104 - compatible
105 - reg
106 - "#address-cells"
107 - "#size-cells"
108 - ranges
109 - clocks
110 - clock-names
111 - resets
112 - reset-names
117 - if:
122 - qcom,msm8998-qmp-pcie-phy
127 clock-names:
129 - const: aux
130 - const: cfg_ahb
131 - const: ref
134 reset-names:
136 - const: phy
137 - const: common
139 - vdda-phy-supply
140 - vdda-pll-supply
142 - if:
147 - qcom,ipq6018-qmp-pcie-phy
148 - qcom,ipq8074-qmp-gen3-pcie-phy
149 - qcom,ipq8074-qmp-pcie-phy
154 clock-names:
156 - const: aux
157 - const: cfg_ahb
160 reset-names:
162 - const: phy
163 - const: common
165 - if:
170 - qcom,sc8180x-qmp-pcie-phy
171 - qcom,sdm845-qhp-pcie-phy
172 - qcom,sdm845-qmp-pcie-phy
173 - qcom,sdx55-qmp-pcie-phy
174 - qcom,sm8250-qmp-gen3x1-pcie-phy
175 - qcom,sm8250-qmp-gen3x2-pcie-phy
176 - qcom,sm8250-qmp-modem-pcie-phy
177 - qcom,sm8450-qmp-gen3x1-pcie-phy
178 - qcom,sm8450-qmp-gen4x2-pcie-phy
183 clock-names:
185 - const: aux
186 - const: cfg_ahb
187 - const: ref
188 - const: refgen
191 reset-names:
193 - const: phy
195 - vdda-phy-supply
196 - vdda-pll-supply
198 - if:
203 - qcom,sm8250-qmp-gen3x2-pcie-phy
204 - qcom,sm8250-qmp-modem-pcie-phy
205 - qcom,sm8450-qmp-gen4x2-pcie-phy
208 "^phy@[0-9a-f]+$":
212 - description: TX lane 1
213 - description: RX lane 1
214 - description: PCS
215 - description: TX lane 2
216 - description: RX lane 2
217 - description: PCS_MISC
219 - if:
224 - qcom,sc8180x-qmp-pcie-phy
225 - qcom,sdm845-qmp-pcie-phy
226 - qcom,sdx55-qmp-pcie-phy
227 - qcom,sm8250-qmp-gen3x1-pcie-phy
228 - qcom,sm8450-qmp-gen3x1-pcie-phy
231 "^phy@[0-9a-f]+$":
235 - description: TX
236 - description: RX
237 - description: PCS
238 - description: PCS_MISC
240 - if:
245 - qcom,ipq6018-qmp-pcie-phy
246 - qcom,ipq8074-qmp-pcie-phy
247 - qcom,msm8998-qmp-pcie-phy
248 - qcom,sdm845-qhp-pcie-phy
251 "^phy@[0-9a-f]+$":
255 - description: TX
256 - description: RX
257 - description: PCS
260 - |
261 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
262 phy-wrapper@1c0e000 {
263 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
265 #address-cells = <1>;
266 #size-cells = <1>;
273 clock-names = "aux", "cfg_ahb", "ref", "refgen";
276 reset-names = "phy";
278 vdda-phy-supply = <&vreg_l10c_0p88>;
279 vdda-pll-supply = <&vreg_l6b_1p2>;
291 #clock-cells = <0>;
292 clock-output-names = "pcie_1_pipe_clk";
294 #phy-cells = <0>;