Lines Matching +full:otg +full:- +full:vbus

1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-rockchip-inno-usb2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
15 - rockchip,px30-usb2phy
16 - rockchip,rk3128-usb2phy
17 - rockchip,rk3228-usb2phy
18 - rockchip,rk3308-usb2phy
19 - rockchip,rk3328-usb2phy
20 - rockchip,rk3366-usb2phy
21 - rockchip,rk3399-usb2phy
22 - rockchip,rk3568-usb2phy
23 - rockchip,rv1108-usb2phy
28 clock-output-names:
32 "#clock-cells":
38 clock-names:
41 assigned-clocks:
45 assigned-clock-parents:
48 Select between usb-phy output 480m and xin24m.
49 Refer to clk/clock-bindings.txt for generic clock consumer properties.
53 Phandle to the extcon device providing the cable state for the otg phy.
63 When set the driver will request its phandle as one companion-grf
66 host-port:
71 "#phy-cells":
78 interrupt-names:
81 phy-supply:
83 Phandle to a regulator that provides power to VBUS.
84 See ./phy-bindings.txt for details.
87 - "#phy-cells"
89 otg-port:
94 "#phy-cells":
101 interrupt-names:
103 - const: linestate
104 - const: otg-mux
105 - items:
106 - const: otg-bvalid
107 - const: otg-id
108 - const: linestate
110 phy-supply:
112 Phandle to a regulator that provides power to VBUS.
113 See ./phy-bindings.txt for details.
116 - "#phy-cells"
119 - compatible
120 - reg
121 - clock-output-names
122 - "#clock-cells"
123 - host-port
124 - otg-port
127 - if:
131 const: rockchip,rk3568-usb2phy
135 host-port:
139 otg-port:
144 - interrupts
150 host-port:
152 - interrupts
153 - interrupt-names
155 otg-port:
157 - interrupts
158 - interrupt-names
163 - |
164 #include <dt-bindings/clock/rk3399-cru.h>
165 #include <dt-bindings/interrupt-controller/arm-gic.h>
166 #include <dt-bindings/interrupt-controller/irq.h>
168 compatible = "rockchip,rk3399-usb2phy";
171 clock-names = "phyclk";
172 clock-output-names = "clk_usbphy0_480m";
173 #clock-cells = <0>;
175 u2phy0_host: host-port {
177 interrupt-names = "linestate";
178 #phy-cells = <0>;
181 u2phy0_otg: otg-port {
185 interrupt-names = "otg-bvalid", "otg-id", "linestate";
186 #phy-cells = <0>;