Lines Matching +full:usb +full:- +full:misc +full:- +full:reg
1 MediaTek XS-PHY binding
2 --------------------------
4 The XS-PHY controller supports physical layer functionality for USB3.1
8 - compatible : should be "mediatek,<soc-model>-xsphy", "mediatek,xsphy",
9 soc-model is the name of SoC, such as mt3611 etc;
12 - "mediatek,mt3611-xsphy"
14 - #address-cells, #size-cells : should use the same values as the root node
15 - ranges: must be present
18 - reg : offset and length of register shared by multiple U3 ports,
21 - mediatek,src-ref-clk-mhz : u32, frequency of reference clock for slew rate
23 - mediatek,src-coef : u32, coefficient for slew rate calibrate, depends on
26 Required nodes : a sub-node is required for each port the controller
28 'reg' property is used inside these nodes to describe
32 - reg : address and length of the register set for the port.
33 - clocks : a list of phandle + clock-specifier pairs, one for each
34 entry in clock-names
35 - clock-names : must contain
39 - #phy-cells : should be 1
41 - PHY_TYPE_USB2
42 - PHY_TYPE_USB3
46 - mediatek,eye-src : u32, the value of slew rate calibrate
47 - mediatek,eye-vrt : u32, the selection of VRT reference voltage
48 - mediatek,eye-term : u32, the selection of HS_TX TERM reference voltage
49 - mediatek,efuse-intr : u32, the selection of Internal Resistor
52 - mediatek,efuse-intr : u32, the selection of Internal Resistor
53 - mediatek,efuse-tx-imp : u32, the selection of TX Impedance
54 - mediatek,efuse-rx-imp : u32, the selection of RX Impedance
57 -------------------------------------------------------------
59 u2 port0 0x0000 MISC
62 u2 port1 0x1000 MISC
65 u2 port2 0x2000 MISC
85 u3phy: usb-phy@11c40000 {
86 compatible = "mediatek,mt3611-xsphy", "mediatek,xsphy";
87 reg = <0 0x11c43000 0 0x0200>;
88 mediatek,src-ref-clk-mhz = <26>;
89 mediatek,src-coef = <17>;
90 #address-cells = <2>;
91 #size-cells = <2>;
94 u2port0: usb-phy@11c40000 {
95 reg = <0 0x11c40000 0 0x0400>;
97 clock-names = "ref";
98 mediatek,eye-src = <4>;
99 #phy-cells = <1>;
102 u3port0: usb-phy@11c43000 {
103 reg = <0 0x11c43400 0 0x0500>;
105 clock-names = "ref";
106 mediatek,efuse-intr = <28>;
107 #phy-cells = <1>;